参数资料
型号: FDMA7670
厂商: Fairchild Semiconductor
文件页数: 4/6页
文件大小: 0K
描述: MOSFET N-CH 30V 6-MLP 2X2
标准包装: 3,000
系列: PowerTrench®
FET 型: MOSFET N 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 30V
电流 - 连续漏极(Id) @ 25° C: 11A
开态Rds(最大)@ Id, Vgs @ 25° C: 15 毫欧 @ 11A,10V
Id 时的 Vgs(th)(最大): 3V @ 250µA
闸电荷(Qg) @ Vgs: 22nC @ 10V
输入电容 (Ciss) @ Vds: 1360pF @ 15V
功率 - 最大: 900mW
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
供应商设备封装: 6-MLP(2x2)
包装: 带卷 (TR)
Typical Characteristics T J = 25°C unless otherwise noted
10
I D = 11 A
3000
8
6
4
V DD = 10 V
V DD = 15 V
V DD = 20 V
1000
100
C iss
C oss
2
f = 1 MHz
V GS = 0 V
C rss
0
0
5
10
15
20
10
0.1
1
10
30
Q g , GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
100
1000
V DS , DRAIN TO SOURCE VOLTAGE (V)
Figure 8. Capacitance vs Drain
to Source Voltage
SINGLE PULSE
V GS = 10 V
R θ JA = 145 o C/W
10
0.1 ms
100
T A = 25 o C
1 ms
1
0.1
THIS AREA IS
LIMITED BY r DS(on)
SINGLE PULSE
T J = MAX RATED
R θ JA = 145 o C/W
T A = 25 o C
10 ms
100 ms
1s
10 s
DC
10
1
10
10
10
10
0.01
0.01
0.1
1
10
100
0.1
-4
-3
-2
-1
1
10
100
1000
2
V DS , DRAIN to SOURCE VOLTAGE (V)
Figure 9. Forward Bias Safe
Operating Area
t, PULSE WIDTH (sec)
Figure 10. Single Pulse Maximum
Power Dissipation
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
R θ JA = 145 C/W
0.01
0.05
0.02
0.01
SINGLE PULSE
o
P DM
t 1
t 2
NOTES:
DUTY FACTOR: D = t 1 /t 2
PEAK T J = P DM x Z θ JA x R θ JA + T A
10
10
10
10
0.001
-4
-3
-2
-1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 11. Transient Thermal Response Curve
?2012 Fairchild Semiconductor Corporation
FDMA7670 Rev.C 5
4
www.fairchildsemi.com
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