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参数资料
| 型号： | FDMB668P |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/6页 |
| 文件大小： | 0K |
| 描述： | MOSFET P-CH 20V 6.1A MICROFET8 |
| 产品目录绘图： | MicroFET 3.0 x 1.9 Pkg |
| 标准包装： | 1 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET P 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 20V |
| 电流 - 连续漏极(Id) @ 25° C： | 6.1A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 35 毫欧 @ 6.1A，4.5V |
| Id 时的 Vgs(th)（最大）： | 1V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 59nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 2085pF @ 10V |
| 功率 - 最大： | 800mW |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-MLP，MicroFET? |
| 供应商设备封装： | 8-MLP，MicroFET（3x1.9） |
| 包装： | 标准包装 |
| 产品目录页面： | 1609 (CN2011-ZH PDF) |
| 其它名称： | FDMB668PDKR |
Electrical Characteristics T J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
? BV DS S
? T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = -250 μ A, V GS = 0V
I D = -250 μ A, referenced to 25°C
V DS = -16V, V GS = 0V
V GS = ±8V, V DS = 0V
-20
-11.4
-1
±100
V
mV/° C
μ A
nA
On Characteristics (Note 2)
V GS(th)
? V GS(th)
? T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = -250 μ A
I D = -250 μ A, referenced to 25°C
-0.4
-0.6
2.8
-1.0
V
mV/°C
V GS = -4.5V, I D = -6.1A
22
35
r DS(on)
Static Drain to Source On Resistance
V GS = -2.5V, I D = -5.1A
V GS = -1.8V, I D = -4.3A
27
35
50
70
m ?
V GS = -4.5V, I D = -6.1A,T J = 125°C
31
50
g FS
Forward Transconductance
V DS = -4.5V, I D = -6.1A
27
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = -10V, V GS = 0V,
f = 1MHz
1565
210
175
2085
280
265
pF
pF
pF
Switching Characteristics
t d(on)
t r
t d(off)
t f
Q g
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
V DD = -10V, I D = -6.1A
V GS = -4.5V, R GEN = 6 ?
V GS = 0V to -10V
7
9
176
84
42
14
18
282
135
59
ns
ns
ns
ns
nC
Q g
Q gs
Total Gate Charge
Gate to Source Gate Charge
V GS = 0V to -5V
V DD = -10V
I D = -6.1A
22
3
31
nC
nC
Q gd
Gate to Drain “Miller” Charge
5
nC
Drain-Source Diode Characteristics
V SD
Source to Drain Diode Forward Voltage
V GS = 0V, I S = -1.6A
(Note 2)
-0.7
-1.2
V
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
I F = -6.1A, di/dt = 100A/ μ s
29
15
44
23
ns
nC
Notes:
1: R θ JA is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R θ JC is guaranteed by design while R θ JA is determined by the user ’s board design.
2: Pulse Test: Pulse Width < 300 us, Duty Cycle < 2%.
a) 65°C/W when mounted on a
1in 2 pad of 2 oz copper
b) 165°C/W when mounted on a
minimum pad .
FDMB668P Rev.B
2
www.fairchildsemi.com
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