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参数资料
| 型号： | FDMC8588 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/7页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 25V 17A 8-MLP |
| 标准包装： | 3,000 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 25V |
| 电流 - 连续漏极(Id) @ 25° C： | 17A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 5 毫欧 @ 18A，10V |
| Id 时的 Vgs(th)（最大）： | 1.8V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 12nC @ 4.5V |
| 输入电容 (Ciss) @ Vds： | 1695pF @ 13V |
| 功率 - 最大： | 3W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-PowerVDFN |
| 供应商设备封装： | 8-PQFN（3.3X3.3），Power33 |
| 包装： | 带卷 (TR) |
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DSS
Δ T J
I DSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
I D = 250 μ A , V GS = 0 V
I D = 250 μ A , referenced to 25 °C
V DS = 20 V, V GS = 0 V
25
17
1
V
mV/°C
μ A
I GSS
Gate to Source Leakage Current, Forward V GS = 12 V, V DS = 0 V
100
nA
On Characteristics
V GS(th)
Δ V GS(th)
Δ T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
I D = 250 μ A , referenced to 25 °C
0.8
1.4
-4
1.8
V
mV/°C
V GS = 10 V, I D = 17 A
3.5
5.0
r DS(on)
Static Drain to Source On Resistance
V GS = 4.5 V, I D = 16.5 A
4.3
5.7
m Ω
V GS = 10 V, I D = 17 A,T J = 125 °C
4.8
6.9
g FS
Forward Transconductance
V DD = 5 V, I D = 16.5 A
85
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = 13 V, V GS = 0 V,
f = 1 MHz
1228
441
69
0.5
pF
pF
pF
Ω
Switching Characteristics
t d(on)
Turn-On Delay Time
8
ns
t r
t d(off)
t f
Q g(TOT)
Q gs
Q gd
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge at 4.5V
Total Gate Charge
Gate to Drain “Miller” Charge
V DD = 13 V, I D = 16.5A,
V GS = 10 V, R GEN = 6 Ω
V DD = 13 V, I D = 16.5 A
3
25
2
12
3.0
3.3
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics
V SD
t rr
Q rr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V GS = 0 V, I S = 2 A
V GS = 0 V, I S = 16.5 A
I F = 16.5 A, di/dt = 100 A/ μ s
(Note 2)
(Note 2)
0.7
0.8
25
10
1.2
1.2
V
V
ns
nC
Notes:
1. R θ JA is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R θ JC is guaranteed by design while R θ CA is determined by
the user's board design.
a. 53 °C/W when mounted on a
1 in 2 pad of 2 oz copper
b. 125 °C/W when mounted on
a minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0%.
3. E AS of 29 mJ is based on starting T J = 25 ° C, L = 1.2 mH, I AS = 7 A, V DD = 23 V, V GS = 10V. 100% tested at L = 0.1 mH, I AS = 16 A.
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
5. The continuous Vds rating is 25V; however, a pulse of 28 V peak voltage for no longer than 3ns duration at 500KHz frequency can be applied.
?2012 Fairchild Semiconductor Corporation
FDMC8588 Rev.D3
2
www.fairchildsemi.com
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