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| 型号： | FDMC86116LZ |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/7页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 100V 3.3A 8-MLP |
| 标准包装： | 3,000 |
| 系列： | PowerTrench® |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 100V |
| 电流 - 连续漏极(Id) @ 25° C： | 3.3A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 103 毫欧 @ 3.3A，10V |
| Id 时的 Vgs(th)（最大）： | 2.2V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 6nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 310pF @ 50V |
| 功率 - 最大： | 2.3W |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DS S
Δ T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = 250 μ A, V GS = 0 V
I D = 250 μ A, referenced to 25 °C
V DS = 80 V, V GS = 0 V
V GS = ±20 V, V DS = 0 V
100
73
1
±10
V
mV/°C
μ A
μ A
On Characteristics
V GS(th)
Δ V GS(th )
Δ T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
I D = 250 μ A, referenced to 25 °C
1.0
1.8
-6
2.2
V
mV/°C
V GS = 10 V, I D = 3.3 A
79
103
r DS(on)
Static Drain to Source On Resistance
V GS = 4.5 V, I D = 2.7 A
105
153
m Ω
V GS = 10 V, I D = 3.3 A, T J = 125 °C
136
178
g FS
Forward Transconductance
V DS = 5 V, I D = 3.3 A
11
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = 50 V, V GS = 0 V,
f = 1 MHz
232
45
2.4
0.7
310
60
5
pF
pF
pF
Ω
Switching Characteristics
t d(on)
Turn-On Delay Time
4.5
10
ns
t r
t d(off)
t f
Q g(TOT)
Q g(TOT)
Q gs
Q gd
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Total Gate Charge
Gate to Drain “Miller” Charge
V DD = 50 V, I D = 3.3 A,
V GS = 10 V, R GEN = 6 Ω
V GS = 0 V to 10 V
V GS = 0 V to 4.5 V V DD = 50 V,
I D = 3.3 A
1.3
10
1.4
4
2
0.8
0.7
10
20
10
6
3
ns
ns
ns
nC
nC
nC
nC
Drain-Source Diode Characteristics
V SD
t rr
Q rr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V GS = 0 V, I S = 3.3 A
V GS = 0 V, I S = 2 A
I F = 3.3 A, di/dt = 100 A/ μ s
(Note 2)
(Note 2)
0.85
0.82
33
23
1.3
1.2
54
38
V
ns
nC
NOTES:
1. R θ JA is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R θ JC is guaranteed by design while R θ CA is determined by
the user's board design.
a. 53 °C/W when mounted on a
1 in 2 pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0%.
3. Starting T J = 25 ° C; N-ch: L = 1.0 mH, I AS = 5.0 A, V DD = 90 V, V GS = 10 V.
4. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
b. 125 °C/W when mounted on
a minimum pad of 2 oz copper
?2011 Fairchild Semiconductor Corporation
FDMC86116LZ Rev.C2
2
www.fairchildsemi.com
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