参数资料
型号: FDMS9620S
厂商: Fairchild Semiconductor
文件页数: 5/9页
文件大小: 0K
描述: MOSFET N-CHAN DUAL 30V POWER56
产品目录绘图: 8-MLP, Power33, 56 Dual
标准包装: 1
系列: PowerTrench®
FET 型: 2 个 N 沟道(双)
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 30V
电流 - 连续漏极(Id) @ 25° C: 7.5A,10A
开态Rds(最大)@ Id, Vgs @ 25° C: 21.5 毫欧 @ 7.5A,10V
Id 时的 Vgs(th)(最大): 3V @ 250µA
闸电荷(Qg) @ Vgs: 14nC @ 10V
输入电容 (Ciss) @ Vds: 665pF @ 15V
功率 - 最大: 1W
安装类型: 表面贴装
封装/外壳: 8-MLP,Power56
供应商设备封装: Power56
包装: 标准包装
产品目录页面: 1609 (CN2011-ZH PDF)
其它名称: FDMS9620SDKR
Typical Characteristics (Q1 N-Channel) T J = 25°C unless otherwise noted
10
I D = 7.5A
V DD =10V
1000
8
C iss
6
4
V DD = 15V
V DD = 20V
100
C oss
2
f = 1MHz
V GS = 0V
C rss
0
0
2
4
6
8
10
12
30
0.1
1
10
30
Q g , GATE CHARGE(nC)
Figure 7. Gate Charge Characteristics
V DS , DRAIN TO SOURCE VOLTAGE (V)
Figure 8. Capacitance vs Drain
to Source Voltage
100
10
100
V GS = 10V
1
SINGLE PULSE
T J = MAX RATE
1ms
10ms
10
R θ JA = 120 C/W
T A = 25 C
0.1
R θ JA = 120 o C
T A = 25 o C
THIS AREA IS LIMITED
BY r DS(ON)
100ms
1s
10s
DC
1
SINGLE PULSE
o
o
10
10
10
10
10
10
10
0.01
0.1
1
10
100
0.5
-3
-2
-1
0
1
2
3
2
V DS , DRAIN to SOURCE VOLTAGE (V)
Figure 9. Forward Bias Safe
Operating Area
t, PULSE WIDTH (s)
Figure 10. Single Pulse Maximum
Power Dissipation
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
P DM
0.1
0.01
t 1
t 2
R θ JA = 120 C/W
SINGLE PULSE
o
NOTES:
DUTY FACTOR: D = t 1 /t 2
PEAK T J = P DM x Z θ JA x R θ JA + T A
10
10
10
10
10
10
10
0.01
-3
-2
-1
0
1
2
3
t, RECTANGULAR PULSE DURATION (s)
Figure 11. Transient Thermal Response Curve
?2007 Fairchild Semiconductor Corporation
FDMS9620S Rev.D2
5
www.fairchildsemi.com
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