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参数资料
| 型号： | FDP5500 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 5/7页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 55V 80A TO-220AB |
| 标准包装： | 50 |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 标准 |
| 漏极至源极电压(Vdss)： | 55V |
| 电流 - 连续漏极(Id) @ 25° C： | 80A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 7 毫欧 @ 80A，10V |
| Id 时的 Vgs(th)（最大）： | 4V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 269nC @ 20V |
| 输入电容 (Ciss) @ Vds： | 3565pF @ 25V |
| 功率 - 最大： | 375W |
| 安装类型： | 通孔 |
| 封装/外壳： | TO-220-3 |
| 供应商设备封装： | TO-220-3 |
| 包装： | 管件 |
Typical Characteristics
1000
1000
100
10
100us
1ms
100
If R = 0
t AV = (L)(I AS )/(1.3*RATED BV DSS - V DD )
If R ≠ 0
t AV = (L/R)ln[(I AS *R)/(1.3*RATED BV DSS - V DD ) +1]
STARTING T J = 25 o C
1
LIMITED
BY PACKAGE
OPERATION IN THIS SINGLE PULSE
10ms
DC
10
STARTING T J = 150 o C
AREA MAY BE
T J = MAX RATED
T C = 25 o C
0.1
1
LIMITED BY rDS (on)
10 100
V DS , DRAIN TO SOURCE VOLTAGE (V)
200
1
0.01
0.1
1 10 100
t AV , TIME IN AVALANCHE (ms)
1000 5000
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching
Capability
160
120
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
V DD = 5V
160
120
PULSE DURATION = 80 μ s
V GS = 10V DUTY CYCLE = 0.5% MAX
V GS = 6V
V GS = 5.5V
80
T J = 175 o C
80
40
T J = 25 o C
T J = -55 o C
40
V GS = 5V
V GS = 4.5V
0
0
1 2 3 4 5 6
7
0
0
1 2 3 4
5
40
V GS , GATE TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
V DS , DRAIN TO SOURCE VOLTAGE (V)
Figure 8. Saturation Characteristics
2.2
30
I D = 80A
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
2.0
1.8
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
1.6
20
10
T J = 175 o C
1.4
1.2
1.0
0
4
T J = 25 o C
6 8
V GS , GATE TO SOURCE VOLTAGE (V)
10
0.8
0.6
-80
I D = 80A
V GS = 10V
-40 0 40 80 120 160
T J , JUNCTION TEMPERATURE ( o C )
200
Figure 9. Drain to Source On-Resistance
Variation vs Gate to Source Voltage
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
FDP5500_F085 Rev. A
5
www.fairchildsemi.com
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