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参数资料
| 型号： | FDPC8011S |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 12/15页 |
| 文件大小： | 0K |
| 描述： | MOSF DL N CH ASYM 25V PWR CLIP33 |
| 标准包装： | 1 |
| 系列： | PowerTrench® |
| FET 型： | 2 N 沟道（双）非对称型 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 25V |
| 电流 - 连续漏极(Id) @ 25° C： | 13A，27A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 6 毫欧 @ 13A，10V |
| Id 时的 Vgs(th)（最大）： | 2.2V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 19nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 1240pF @ 13V |
| 功率 - 最大： | 800mW，900mW |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WDFN 裸露焊盘 |
| 供应商设备封装： | 8-PQFN（3.3X3.3），Power33 |
| 包装： | 标准包装 |
| 其它名称： | FDPC8011SFSDKR |
Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Clip is a high power density solution and all high current flow paths, such as V+(HSD), SW and GND(LSS) should be
short and wide for minimal resistance and inductance. V+(HSD) and GND(LSS) are the primary heat flow paths for the Power Clip.
A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part.
Figure 3.Top/Component (green) View and Bottom (red) PCB View
Following is a guideline, not a requirement which the PCB designer should consider.
Figure 3 shows an example of a well designed layout. The discussion that follows summarizes the key features of this layout.
"The input ceramic bypass capacitor between VIN and GND should be placed as close as possible to the pins V+ / V+(HSD) PAD
and GND / GND(LSS) PAD to help reduce parasitic inductance and high frequency ringing. Several capacitors may be placed in
parallel, and capacitors may be placed on both the top and bottom side of the board. The capacitor located immediately adjacent
to the Power Clip will be the most effective at reducing HF parasitic. Caps located farther away, or on the opposite side of the board
will also assist, but will be less effective due to increased trace inductance.
"The Power Clip package design, with very short distance between pins V+ and GND, allows for a short connect distance to the
input cap. This is a factor that enables the Power Clip switch loop to have very low parasitic inductance.
"Use large copper areas on the component side to connect the V+ pin and V+ (HSD) pad, and the GND and GND(LSS) PAD.
"The SW to inductor copper trace is a high current path. It will also be a high noise region due to switching voltage transients. The
trace should be short and wide to enable a low resistance path and to minimize the size of the noise region. Care should be taken
to minimize coupling of this trace to adjacent traces. The layout in Figure 3 shows a good example of this short, wide path.
"The Power Trench ? Technology MOSFETs used in the Power Clip are effective at minimizing SW node ringing. They incorporate
a proprietary design 1 that minimizes the peak overshoot ring voltage on the switch node (SW). They allow the part to operate well
within the breakdown voltage limits. For most layouts, this eliminates the need to add an external snubber circuit. If the designer
chooses to use an RC snubber, it should be placed close to the part between the SW pins and GND / GND (LSS) PAD to dampen
the high frequency ringing.
"The Driver IC should be placed relatively closed to HSG pin and LSG pin to minimize G drive trace inductance. Excessive G trace
length may slow the switching speed of the HS drive. And it may lead to excessive ringing on the LS G. If the designer must place
the driver a significant distance away from the Power Clip, it would be a good practice to include a 0 Ohm resistor in the LS G path
as a place holder. In the final design, if the LS G exhibits excessive LF ringing, efficiency can often be improved by changing this
resistor to a few Ohms to dampen the LS G LF ringing.
"The Power Clip has very good Junction-PCB heat transfer from all power pins. It has much better heat transfer Junction-GND (LSS)
than traditional dual FET packages. In most cases, board ground will be the most effective heat transfer path on the PCB. Use a
large copper area between GND / GND(LSS)PAD pins and board ground. To ensure the best thermal and electrical connection to
ground, we recommend using multiple vias to interconnect ground plane layers as shown in Figure 3.
1.Patent Pending
?2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C5
12
www.fairchildsemi.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| FDPC8012S | 功能描述:MOSFET 25V Asymmetric Dual N-Channel Pwr Trench RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| FDPC8013S | 功能描述:MOSFET Low Power Two-Input Logic Gate TinyLogic RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| FDPC8014S | 制造商:Fairchild Semiconductor Corporation 功能描述:PT9N 30/12 & PT9N 25/12S PWRCLIP |
| FDPC8016S | 制造商:Fairchild Semiconductor Corporation 功能描述:PT9N 30/12 & PT9N 25/12S IN PWRC |
| FDPF 4001 EH | 制造商:FIBRE DATA 功能描述:FIBRE POLYMER 20M 1 CORE 制造商:FIBRE DATA 功能描述:FIBRE, POLYMER, 20M, 1 CORE 制造商:FIBRE DATA 功能描述:FIBER OPTIC CABLE; Reel Length (Imperial):65.62ft; Reel Length (Metric):20m; Fiber Diameter:5mm; No. of Fibers:1; Jacket Color:-; Jacket Material:PE (Polyethylene); External Diameter:2.2mm ;RoHS Compliant: Yes |
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