参数资料
型号: FDS8949
厂商: Fairchild Semiconductor
文件页数: 2/6页
文件大小: 0K
描述: MOSFET N-CH DUAL 40V 6A 8-SOIC
产品变化通告: Mold Compound Change 12/Dec/2007
标准包装: 1
系列: PowerTrench®
FET 型: 2 个 N 沟道(双)
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 40V
电流 - 连续漏极(Id) @ 25° C: 6A
开态Rds(最大)@ Id, Vgs @ 25° C: 29 毫欧 @ 6A,10V
Id 时的 Vgs(th)(最大): 3V @ 250µA
闸电荷(Qg) @ Vgs: 11nC @ 5V
输入电容 (Ciss) @ Vds: 955pF @ 20V
功率 - 最大: 900mW
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 标准包装
产品目录页面: 1603 (CN2011-ZH PDF)
其它名称: FDS8949DKR
Electrical Characteristics T J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
Drain to Source Breakdown Voltage I D = 250 μ A, V GS = 0V
40
V
? BV DSS
? T J
I DSS
I GSS
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = 250 μ A, referenced to 25°C
V DS = 32V, V GS = 0V
T J = 55 ° C
V GS = ±20V,V DS = 0V
33
1
10
±100
mV/° C
μ A
μ A
nA
On Characteristics (Note 2)
V GS(th)
? V GS(th )
? T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
I D = 250 μ A, referenced to 25°C
1
1.9
-4.6
3
V
mV/°C
V GS = 10V, I D = 6A
21
29
r DS(on)
Drain to Source On Resistance
V GS = 4.5V, I D = 4.5A
26
36
m ?
V GS = 10V, I D = 6A,T J = 125°C
29
43
g FS
Forward Transconductance
V DS = 10V,I D = 6A
22
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = 20V, V GS = 0V,
f = 1MHz
f = 1MHz
715
105
60
1.1
955
140
90
pF
pF
pF
?
Switching Characteristics
t d(on)
t r
t d(off)
t f
Q g
Q gs
Q gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller”Charge
V DD = 20V, I D = 1A
V GS = 10V, R GEN = 6 ?
V DS = 20V, I D = 6A,V GS = 5V
9
5
23
3
7.7
2.4
2.8
18
10
37
6
11
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
V SD
Source to Drain Diode Forward Voltage V GS = 0V, I S = 6A (note 2)
0.8
1.2
V
t rr
Q rr
Reverse Recovery Time (note 3)
Reverse Recovery Charge
I F = 6A, d iF /d t = 100A/ μ s
17
7
26
11
ns
nC
Notes:
1: R θ JA is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. R θ JC is guaranteed by design while R θ JA is determined by the user ’s board design.
a) 81°C/W when
mounted on a 1in 2
pad of 2 oz copper
Scale 1:1 on letter size paper
2: Pulse Test: Pulse Width < 300 us, Duty Cycle < 2.0%.
3: Starting T J = 25 ° C, L = 1mH, I AS = 7.3A, V DD = 40V, V GS = 10V.
b) 135°C/W when mounted on a
minimum pad .
FDS8949 Rev. B1
2
www.fairchildsemi.com
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