参数资料
型号: GT-48006A
厂商: Galileo Technology Services, LLC
英文描述: Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、双端口10/100Mbps以太网桥式/交换式控制器)
中文描述: 低成本双口10/100Mbps以太网桥/开关控制器(低成本,双端口10/100以太网桥式/交换式控制器)
文件页数: 12/33页
文件大小: 352K
代理商: GT-48006A
GT-48006A Low Cost Two Port 10/100 Ethernet Bridge/Switch Controller
2
1.
Functional Overview
The GT-48006A is a high-performance/low-cost, two-port 10/100Mbps Ethernet bridge/switch that provides packet
switching/bridging functions between two on-chip 10/100Mbps auto-negotiated ports. The GT-48006A is intended for
applications that need to bridge between two 10/100BaseX collision domains, such as:
Autonegotiating “dual speed” 10/100 repeaters
Unmanaged 10/100 bridges
Fiber to 100BaseTX media converters
The GT-48006A provides no network management functions (other than LEDs). OEMs requiring management should
consider the GT-48002A and GT-48004A 100BaseTX switches, or Galileo’s GalaxyTM Family of low-cost desktop
switching components (the GT-48212 and GT-48208.)
1.1
Fast Ethernet Ports
The GT-48006A integrates two Fast Ethernet ports each capable of operation at 10/100Mbps (half-duplex) or 20/
200Mbps (full-duplex). Two Media Independent Interfaces (MII) are provided for glueless connection to off-the-shelf
PHY chips. The GT-48006A supports full auto-negotiation for capable PHYs. The speed (10 or 100 Mbps) and duplex
(half or full) to which the PHY resolves to operate is automatically reported to the GT-48006A. The port can also be
forced to operate in a specific duplex mode, if so desired. Each port includes the Media Access Control function (MAC);
the serial LED and MDC/MDIO interface is shared between the ports.
The Fast Ethernet ports support backpressure in half-duplex mode. When backpressure is enabled, and there is no
receive buffer available for incoming traffic, the GT-48006A will force a JAM pattern on the receiving port.
1.2
Address Recognition
The GT-48006A can recognize up to 16,000 different Unicast MAC addresses and unlimited Multicast/Broadcast MAC
addresses. An intelligent address recognition mechanism enables filtering and forwarding packets at full Fast Ethernet
wire speed.
1.3
DRAM Interface
GT-48006A interfaces directly to 1Mbyte or 2Mbyte of EDO DRAM. The DRAM is used to store the incoming/outgoing
packets as well as the address table and other device data structures. The interface to EDO DRAM is glueless; all sig-
nals needed to control EDO devices are provided.
1.4
Packet Buffers
Incoming packets are buffered in the DRAM array. These buffers provide elastic storage for transferring data between
low-speed and high-speed segments. The packet buffers are managed automatically by the GT-48006A.
相关PDF资料
PDF描述
GT-48207 Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器)
GT-48208 Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器)
GT-48212 Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器)
GT-64010A System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(带PCI接口用于R4XXX/ R5000 系列 CPUs的系统控制器)
GT-64012 Secondary Cache Controller For the MIPS R4600/4650/4700/5000,(用于MIPS R4600/4650/4700/5000处理器的二级高速缓存控制器)
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