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| 型号： | GT-48006A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、双端口10/100Mbps以太网桥式/交换式控制器) |
| 中文描述： | 低成本双口10/100Mbps以太网桥/开关控制器（低成本，双端口10/100以太网桥式/交换式控制器） |
| 文件页数： | 33/33页 |
| 文件大小： | 352K |
| 代理商： | GT-48006A |
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GT-48006A Low Cost Two Port 10/100 Ethernet Bridge/Switch Controller
9
5.
Operational Overview
The GT-48006A uses a “store-and-forward” switching approach. Store-and-forward was chosen for the following rea-
sons:
Store-and-forward switches allow switching between differing speed media (e.g. 10BaseX and 100BaseX.)
Such switches require the large elastic buffers that are provided by the EDO DRAM arrays. This is especially
true when bridging between a server on a 100Mbps network and clients on a 10Mbps segment.
Store-and-forward switches improve overall network performance by acting as a “network cache”, effectively
buffering packets during times of heavy congestion.
Store-and-forward switches prevent the forwarding of corrupted packets by analyzing the frame check
sequence (FCS) before forwarding to the destination port.
5.1
Basic Operation
The basic operation of the GT-48006A is quite simple. The GT-48006A receives incoming packets from one of its
ports, searches in the Address Table for the Destination MAC Address and then forwards the packet to the other port, if
appropriate.
If the destination address and source address are not found in the other port’s address table, the GT-48006A treats the
packet as a multicast packet and forwards the packet to the other port.
The GT-48006A automatically learns the port number of attached network devices by examining the Source MAC
Address of all incoming packets. If the Source Address is not found in the GT-48006A’s Address Table, the device adds
it to the table.
5.2
Address Learning
The GT-48006A can learn up to 8K unique MAC addresses. Addresses are stored in the Address Table located in
DRAM. The Address Table is managed automatically by the GT-48006A (i.e. new addresses are automatically added
to the Address Table). The GT-48006A’s address learning process is outlined in Section 6.
5.3
Packet Buffering
The GT-48006A supports up to 1008 full packet size receive buffers. These buffers can be dynamically allocated to the
two receive ports or can be optionally limited on a per port basis. When working in dynamic buffer allocation mode, the
GT-48006A supports 1008 buffers in 2Mbyte DRAM configuration and 308 buffers in 1Mbyte DRAM configuration. In
fixed buffer mode, the GT-48006A supports 140 buffers per port in 1Mbyte DRAM, and 320 buffers per port in the
2Mbyte configuration. Buffer allocation mode is selected via a RESET strapping option as shown in Table 1 on page 7.
5.4
Packet Forwarding
Once an address has been learned, and the packet is buffered, it must be forwarded. The packet forwarding mecha-
nism for the GT-48006A is handled automatically based on the destination address.
5.5
Terminology
It is important to understand the basic terminology used to describe the GT-48006A before getting into a detailed
description. Table 2 on page 9 explains the terms used throughout this document.
Table 2: Terminology
Te rm
De fi n i t i on
Address Table
The Address Table is a data structure in the GT-48006A’s DRAM that con-
tains all learned MAC addresses, and routing information associated with
those addresses.
Source Address
The Source Address (SA) is the MAC address from which a received
packet was sent.
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