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| 型号： | GT-48006A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、双端口10/100Mbps以太网桥式/交换式控制器) |
| 中文描述： | 低成本双口10/100Mbps以太网桥/开关控制器（低成本，双端口10/100以太网桥式/交换式控制器） |
| 文件页数： | 9/33页 |
| 文件大小： | 352K |
| 代理商： | GT-48006A |
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GT-48006A Low Cost Two Port 10/100 Ethernet Bridge/Switch Controller
17
Figure 3: MII Receive Signal Timing
Table 4: MII Signal Timings Synchronous to RxClk
9.9
10/100 Mbps Full-Duplex Operation
When operating in Full-duplex mode the GT-48006A can transmit and receive frames simultaneously. In full-duplex
mode, the CrS signal is associated with received frames only and has no effect on transmitted frames. The Col signal
is ignored by the GT-48006A while in Full-duplex mode. Transmission starts when TxEn goes active. Transmission
starts regardless of the state of RxDV. Reception starts when the RxDV signal is asserted indicating traffic on the
receive port of the PHY.
9.10
Illegal Frames
The GT-48006A will discard all illegal frames. Examples include: runts (less than 64 bytes), oversize (greater than
1518 or 1522 bytes), and bad FCS (bad CRC.)
9.11
Backpressure
Backpressure is supported for half-duplex operation. When the GT-48006A cannot allocate a receive buffer for an
incoming packet, the device will transmit a jamming pattern on the port, thus forcing a collision. Backpressure is not
active in full-duplex mode.
Backpressure is enabled via a RESET strapping option as shown in Table 1 on page 7. Backpressure is not active
when dynamic buffer mode is enabled (see Section 7.1).
9.12
VLAN Tagging Support
The GT-48006A will pass 802.1q frames (i.e. frames up to 1522 bytes) if the VL Tag Enable is selected at RESET via
the DAdr[4] pin.
GT-48006A
IE EE 802.3 u Spe c .
Na m e
Pa ra m e te r
MI N
MA X
MIN
MAX
Un its
ts
Setup Time to Rising RxClk
6
10
ns
th
Hold Time after Rising RxClk
1
10
ns
ts
RxClk
RxD, RxDV,
RxEr
th
Vih
min
Vil
max
Vih
min
Vil
max
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