参数资料
型号: GT-48006A
厂商: Galileo Technology Services, LLC
英文描述: Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、双端口10/100Mbps以太网桥式/交换式控制器)
中文描述: 低成本双口10/100Mbps以太网桥/开关控制器(低成本,双端口10/100以太网桥式/交换式控制器)
文件页数: 28/33页
文件大小: 352K
代理商: GT-48006A
GT-48006A Low Cost Two Port 10/100 Ethernet Bridge/Switch Controller
4
3.
Pin Functions and Assignment
S y mbol
Ty p e
D esc ri pti o n
Clock and Reset
Rst*
I
RESET: Active LOW. Rst* must be asserted for at least 10 clock cycles when
in the reset state. Following Rst* deassertion, the GT-48006A clears the inter-
nal buffers and initializes the address table in the DRAM. The address table
initialization takes 165,000 CLK cycles to complete. Any incoming packets dur-
ing address table initialization are ignored.
Clk
I
Clock: Provides the timing for the GT-48006A internal units. All functional
units except for the serial interfaces use this clock.The clock frequency is
40MHz. THIS INPUT IS NOT 5V TOLERANT.
DRAM Interface
DData[31:0]
I/O
DRAM Data: 32-bit EDO DRAM data bus. These signals connect directly to
the data input/output pins of the DRAM devices.
DAddr[8:0]
I/O
DRAM Multiplexed Address Bus: In normal operation, DAddr[8:0] contain
the DRAM multiplexed row/column address. During RESET, these multiplexed
pins are sampled by the GT-48006A to indicate various parameters as follows:
DAddr[0] - Autonegotiation enable for port 0
DAddr[1] - Autonegotiation enable for port 1
DAddr[2] - Skip Init
DAddr[3] - Limit4
DAddr[4] - VL Tag Enable passing
DAddr[5] - DRAM size
DAddr[6] - Full Duplex for port 0
DAddr[7] - Full Duplex for port 0
DAddr[8] - Back Pressure enable
RAS[1:0]*
O
Row Address Strobes: DRAM row address strobes. For the two banks.
CAS*
O
Column Address Strobe: DRAM column address strobe. The GT-48006A
always accesses 32-bit values and does not require a separate CAS* for each
byte.
WE*
O
Write Enable: DRAM write enable.
Media Independent
Interface
TxEn[1:0]
O
Transmit Enable: Active HIGH. This output indicates that the packet is being
transmitted. TxEn is synchronous to TxClk.
TxClk[1:0]
I
Transmit Clock: Provides the timing reference for the transfer of TxEn, TxD
signals. TxClk frequency is one fourth of the data rate (25 MHz for 100Mbps,
2.5 MHz for 10Mbps). TxClk nominal frequency should match the nominal fre-
quency of RxClk for the same port.
TxD0[3:0]
O
Transmit Data 0: Outputs the Port0 Transmit Data. Synchronous to TxClk[0].
TxD1[3:0]
O
Transmit Data 1: Outputs the Port1 Transmit Data. Synchronous to TxClk[1].
Col[1:0]
I
Collision detect: Active HIGH. Indicates a collision has been detected on the
wire. This input is ignored in full-duplex mode. Col is not synchronous to any
clock.
RxD0[3:0]
I
Receive Data 0: Port 0 Receive Data. Synchronous to RxClk[0].
RxD1[3:0]
I
Receive Data 1: Port 1 Receive Data. Synchronous to RxClk[1].
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