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| 型号： | GT-48006A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、双端口10/100Mbps以太网桥式/交换式控制器) |
| 中文描述： | 低成本双口10/100Mbps以太网桥/开关控制器（低成本，双端口10/100以太网桥式/交换式控制器） |
| 文件页数： | 14/33页 |
| 文件大小： | 352K |
| 代理商： | GT-48006A |
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GT-48006A Low Cost Two Port 10/100 Ethernet Bridge/Switch Controller
21
11.
DRAM Interface and Usage
The GT-48006A includes direct support for EDO DRAMs. The performance of EDO satisfies the required bandwidth for
wire-speed data transfer, address recognition and Tx descriptor fetch/update. The DRAM interface is entirely glueless.
All accesses are performed as 32-bits. The DRAM interface is designed for 50ns EDO DRAMs and all timings are guar-
anteed to work with these devices. Refresh is performed automatically by the GT-48006A. Please refer to the EV-
48006 evaluation platform schematics for an example of EDO DRAM design with the GT-48006A.
The GT-48006A requires about 300Kbytes of the DRAM for the address table and other private data structures. The
remainder is used for packet buffers. Following power-up or system RESET, the GT-48006A device creates the MAC
Address Table in DRAM, and initializes all locations in the table to indicate that invalid entries exist in all locations.
Galileo recommends using DRAM with 256K x 16 configuration. When using this configuration, 2 DRAM chips are
required for 1 MByte, and 4 DRAM chips are required for 2 MBytes. If 1 MByte is selected, RAS0* should be connected
to 2 DRAM chips while RAS1* should be left unconnected.
If 2 MBytes is selected, RAS0* will control the first 1MB bank, while RAS1* will activate the second 1MB bank.
DData[31:0], DAddr[8:0], CAS*, and WE* should be connected to both banks.
Using 1 or 2 MBytes of DRAM is entirely up to the architect. 2MBytes increases the size of the Rx Buffer space. This
performance advantage must be weighed against the cost of additional memory.
12.
LED Support
The GT-48006A’s serial LED interface is similar to the 3-pin LED interface of the GT-48001A device which requires a
PAL to interpret the LED bit stream. Galileo provides reference designs and example PAL equations in the LED inter-
face application note available on our website.
12.1
LED Indications Interface Description
Table 9 on page 21 shows the data accessible on the LED Indications Serial Interface for both GT-48006A ports.
12.2
Detailed LED Signal Description
12.2.1 Primary Port Status LED
The Primary Port Status LED provides the following information:
If Link Integrity test failed
Port Status LED blinks once;
else Everything is OK (Port Status LED is ON)
12.2.1.1 Status LED blink timing
Link Integrity test failed, Status LED blinks once. Primary status bit is active for 500 ms every 5s.
Table 9: LED Signals Available
D a ta D escr ipt i o n
Sy mbol ic Sig n al N a me
Ty p e
Primary Port Status LED
primary_port_status
n/a
Transmit data in progress
transmit
dynamic
Receive data in progress
receive
dynamic
Collision active
collision
dynamic
Full/Half duplex
full_duplex
static
Receive Buffer Full
rx_buffer_full
dynamic
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