参数资料
型号: HB56S864ESN-7
元件分类: DRAM
英文描述: 8M X 64 EDO DRAM MODULE, 70 ns, DMA168
封装: DIMM-168
文件页数: 10/34页
文件大小: 338K
代理商: HB56S864ESN-7
HB56S872ESN Series, HB56S864ESN Series
18
EDO Page Mode Read-Modify-Write Cycle
60 ns
70 ns
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
EDO page mode read-modify-write cycle
time
t
HPRWC
68
79
ns
WE delay time from CAS precharge
t
CPW
54
62
ns
14
Notes: 1. AC measurements assume t
T = 2 ns.
2. An initial pause of 200
s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing
RAS-only refresh cycle or CAS-before-RAS
refresh). If the internal refresh counter is used, a minimum of eight
CAS-before-RAS refresh
cycles are required.
3. Operation with the t
RCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if t
RCD ≥ tRAD (max) + tAA (max)- tCAC (max), then access time is controlled
exclusively by t
CAC.
4. Operation with the t
RAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if t
RAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by t
AA.
5. Either t
OED or tCDD must be satisfied.
6. Either t
DZO or tDZC must be satisfied.
7. V
IH (min) and VIL (max) are reference levels for measuring timing of input signals.
Also, transition
times are measured between V
IH (min) and VIL (max).
8. Assumes that t
RCD ≤ tRCD (max) and tRAD ≤ tRAD (max).
If t
RCD or tRAD is greater than the maximum
recommended value shown in this table, t
RAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that t
RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that t
RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either t
RCH or tRRH must be satisfied for a read cycles.
13. t
OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
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