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参数资料
| 型号： | HFA3824AIV |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 封装： | 7 X 7 MM, PLASTIC, TQFP-48 |
| 文件页数： | 10/40页 |
| 文件大小： | 271K |
| 代理商： | HFA3824AIV |
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2-108
TX Port
The transmit data port accepts the data that needs to be
transmitted serially from an external data source. The data is
modulated and transmitted as soon as it is received from the
external data source. The serial data is input to the HFA3824A
through TXD using the falling edge of TXCLK to clock it in the
HFA3824A. TXCLK is an output from the HFA3824A. A timing
scenario of the transmit signal handshakes and sequence is
shown on timing diagram Figures 5 and 6.
The external processor initiates the transmit sequence by
asserting TX_PE. TX_PE envelopes the transmit data packet
on TXD. The HFA3824A responds by generating TXCLK to
input the serial data on TXD. TXCLK will run until TX_PE goes
back to its inactive state indicating the end of the data packet.
TX_PE should be held active at least 3 symbols beyond the
MSB of the data packet to insure modulation by the
HFA3824A. There are two possible transmit scenarios.
One scenario is when the HFA3824A internally generates
the preamble and header information. During this mode the
external source needs to provide only the data portion of the
packet. The timing diagram of this mode is illustrated on
Figure 6. When the HFA3824A generates the preamble
internally, assertion of TX_PE will initialize the generation of
the preamble and header. TX_RDY, which is an output from
the HFA3824A, is used to indicate to the external processor
that the preamble has been generated and the device is
ready to receive the data packet to be transmitted from the
external processor. The TX_RDY timing is programmable in
case the external processor needs several clocks of
advanced notice before actual data transmission is to begin.
The second transmit scenario supported by the HFA3824A
is when the preamble and header information are provided
by the external data source. During this mode TX_RDY is
not required as part of the TX handshake. The HFA3824A
will immediately start transmitting the data available on TXD
upon assertion of TX_PE. The timing diagram of this TX sce-
nario, where the preamble and header are generated exter-
nal to the HFA3824A, is illustrated on Figure 5.
One other signal that can be used for certain applications as
part of the TX interface is the Clear Channel Assessment
(CCA) signal which is an output from the HFA3824A. The CCA
is programmable and it is described with more detail in the
Transmitter section of this document. CCA provides the indica-
tion that the channel is clear of energy and the transmission will
not be subject to collisions. CCA can be monitored by the exter-
nal processor to assist in deciding when to initiate transmis-
sions. The CCA indication can bypassed or ignored by the
external processor. The state of the CCA does not effect the
transmit operation of the HFA3824A. TX_PE alone will always
initiate the transmit state independent of the state of CCA. Sig-
nals TX_RDY, TX_PE and TXCLK can be set individually, by
programming Configuration Register (CR) 9, as either active
high or active low signals.
The transmit port is completely independent from the
operation of the other interface ports including the RX port,
therefore supporting a full duplex mode.
TXCLK
TX_PE
TXD
PREAMBLE - HEADER
MSB OF LAST HEADER FIELD
LSB
DATA PACKET
MSB
NOTE: Preamble/Header and Data is transmitted LSB first TX_RDY is inactive Logic 0 when generated externally. TXD shown generated from rising
edge TXCLK.
FIGURE 5. TX PORT TIMING (EXTERNAL PREAMBLE)
MSB OF LAST HEADER FIELD
LSB
DATA PACKET
MSB
TXCLK
TX_PE
TXD
TX_RDY
NOTE: Preamble/Header and Data is transmitted LSB first TX_RDY is inactive Logic 0 when generated externally. TXD shown generated from rising
edge TXCLK.
FIGURE 6. TX PORT TIMING (INTERNAL PREAMBLE)
HFA3824A
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| HFA3824A | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3842B | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842BIN | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842BIN-TK | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842IN96 | Wireless LAN Medium Access Controller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3824AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3824AIV96 | 制造商:Rochester Electronics LLC 功能描述:BASEBAND PROCESSOR - Bulk |
| HFA3824EVAL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3824IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3824IV96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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