参数资料
型号: HFA3824AIV
厂商: INTERSIL CORP
元件分类: 无绳电话/电话
英文描述: Direct Sequence Spread Spectrum Baseband Processor
中文描述: TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48
封装: 7 X 7 MM, PLASTIC, TQFP-48
文件页数: 27/40页
文件大小: 271K
代理商: HFA3824AIV
2-125
CONFIGURATION REGISTER 2 ADDRESS (08h) MODEM CONFIGURATION REGISTER C
Bit 7, 6
These control bits are used to select the number of chips per symbol used in the I and Q paths of the receiver matched filter
correlators (see table below).
Bit 5
This control bit is used to disable the CRC16 check. When set to a one, the processor will accept the received packet and
any packet error checks will have to be detected externally. When set to a zero, the processor will reset itself to the acqui-
sition mode if the CRC16 calculated by the 3824A does not match the CRC16 in the header.
Logic 1 = Disable Receiver CRC check
Logic 0 = Enable Receiver CRC check
Bit 4, 3
These control bits are used to select the divide ratio for the demodulators receive chip clock timing. The value of N is
determined by the following equation:
Symbol Rate = MCLK/(N x Chips per symbol).
Bit 2
This bit sets the receiver and antenna control logic for single or dual antenna mode. In single antenna, the required preamble
can be reduced as per Figure 15. The ANT_SEL pin will reflect the receivers choice as per CR0 bit-6.
In dual antenna a 126 symbol preamble is required and the ANT_SEL pin will reflect the receivers choice of the antenna,
the antenna that has the best SQ2 value at the time a verify has occurred (see Figure 14).
During acquisition the ANT_SEL pin will toggle as the receiver performs the algorithm described in Figure 14. Once verifi-
cation has occurred, the ANT_SEL pin will reflect the receivers choice of antenna until one of the following occurs.
1. Chip is in half duplex and TX_PE is taken active.
2. RX_PE transitionsfrom low to high, starting the receiverin acquisition mode (receivers choice will remain onthe ANT_SEL
pin when RX_PE is low).
In dual antenna mode, if RX_PE is taken low before a verify has occurred, the ANT_SEL pin will reflect the antenna that has
the best stored SQ2 valued, if a complete antenna dwell did not take place, the stored SQ2 value will be from the last
completed antenna dwell.
Asserting the RESET# pin will reset the stored SQ2 values.
Because a low on RX_PE resets the toggle flop, the ANT_SEL pin will always be High almost immediately after RX_PE rises
(less than 50ns), then go low (about 135ns after RX_PE rises). So the first antenna dwell will always be with antenna B
selected (ANT)_SEL pin low).
Logic 0 = Acquisition processing is for dual antenna acquisition.
Logic 1 = Acquisition processing is for single antenna acquisition.
(If set to a “1”, CR5, bit 6 should be set to a “1”.)
Bit 1, 0
These control bits are used to indicate one of the four Preamble Header modes for receiving data. Each of the modes
includes different combinations of Header fields. Users can choose the mode with the fields that are more appropriate for
their networking requirements. The Header fields that are combined to form the various modes are:
SFD field
CRC16 field
Data length field (indicates the number of data bits that follow the Header information)
Full protocol Header
CHIPS PER SYMBOL
BIT 7
BIT 6
11
0
0
13
0
1
15
1
0
16
1
1
MASTER CLOCK/N
BIT 4
BIT 3
N = 2
0
0
N = 4
0
1
N = 8
1
0
N = 16
1
1
INPUT MODE
BIT 1
BIT 0
RECEIVE PREAMBLE - HEADER FIELDS
0
0
0
Preamble, with SFD Field
1
0
1
Preamble, with SFD, CRC16
2
1
0
Preamble, with SFD Length, CRC16
3
1
1
Preamble, with Full Protocol Header
HFA3824A
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