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参数资料
| 型号： | HFA3824AIV |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 封装： | 7 X 7 MM, PLASTIC, TQFP-48 |
| 文件页数： | 18/40页 |
| 文件大小： | 271K |
| 代理商： | HFA3824AIV |
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2-116
advantage
opposed to a secure communications feature.
Scrambling is done by a polynomial division using a pre-
scribed polynomial. A shift register holds the last quotient
and the output is the exclusive-or of the data and the sum of
taps in the shift register. The taps and seed are programma-
ble. The transmit scrambler seed is programmed by CR 15
and the taps are set with CR 16. Setting the seed is optional,
since the scrambler is self-synchronizing and it will synchro-
nize with the incoming data after flushing the 7 bits stored
from the previous transmission.
as
a
communications
privacy
feature
as
Modulator Description
The modulator is designed to support both DBPSK and
DQPSK signals. The modulator is capable of automatically
switching its rate in the case where the preamble and header
are DBPSK modulated, and the data is DQPSK modulated.
The modulator can support date rates up to 4 MBPS. The
programming details of the modulator are given at the intro-
ductory paragraph of this section. The HFA3824A can sup-
port data rates of up to 4 MBPS (DQPSK).
Clear Channel Assessment (CCA) and
Energy Detect (ED) Description
The clear channel assessment (CCA) circuit implements
the carrier sense portion of a carrier sense multiple access
(CSMA) networking scheme. CCA monitors the environ-
ment to determine when it is feasible to transmit and is
available in real time through output pin 32 of the device.
CCA can be programmed to be a function of RSSI, energy
detected on the channel, or carrier sense or both. CCA is
the logical OR of ED and CSE.
The RSSI (receive signal strength indicator) measures the
energy at the antenna. RSSI is an analog input to the
HFA3824A from the successive IF stage of the radio. A 6-bit
A/D converter is used and its output is compared against a
threshold to produce energy detect (ED). This threshold is
normally set to between -70 and -80dBm. When RXPE is
low, ED will show energy in the channel unless ED is dis-
abled by setting the threshold to all ones. The MAC should
ignore the state of CCA when RXPE is inactive and for sev-
eral microseconds after it becomes active. Once RXPE
becomes active the ED signal will update at 1MHz intervals.
Carrier sense is an indicator used to measure when correlat-
ing PN code has been detected. CSE (carrier sense early) is
active when the SQ1 value is greater than the programmed
threshold. CSE is updated at the end of each antenna dwell
and then after every 64 or 128 symbols as programmed.
CCA (based on CSE) will be valid 17.1
μ
s after RXPE goes
active.
The CCA logic has no effect on the HFA3824A transmit or
receive operations. The active state of the CCA pin is con-
trolled through CR9 (bit 5). CR19 sets the ED threshold,
CR22, CR23, and CR26, CR27 set the thresholds for CSE
as well as CRS (carrier sense) used in acquisition and data
respectively.
In a typical single antenna system CCA will be monitored to
determine when the channel is clear. Once the channel is
detected busy, CCA should be checked periodically to deter-
mine if the channel becomes clear. Once MD_RDY goes
active, CCA can then be ignored until MD_RDY drops. Fail-
ure to monitor CCA until MD_RDY goes active (or use of a
time-out circuit) could result in a stalled system as it is possi-
ble for the channel to be busy and then go clear without an
MD_RDY occurring.
A dual antenna system has the added complexity that CCA
will potentially toggle between active and inactive as each
antenna is checked. The user must avoid mistaking the inac-
tive CCA signals as an indication the channel is clear. Once
the receiver has acquired, CCA should be monitored for loss
of signal until MD_RDY goes active. Monitoring RXCLK for
activity or CRS on the test bus gives sure indications that
acquisition is complete. Alternatively, CCA could be moni-
tored for 3 successive busy indications on either antenna.
Time alignment of CCA monitoring with the receiver’s 16
μ
s
antenna dwells would be required.
Receiver Description
The receiver portion of the baseband processor, performs ADC
conversion and demodulation of the spread spectrum signal.
It correlates the PN spread symbols, then demodulates the
DBPSK or DQPSK symbols. The demodulator includes a
frequency loop that tracks and removes the carrier fre-
quency offset. In addition it tracks the symbol timing, and
differentially decodes and descrambles the data. The data is
output through the RX Port to the external processor.
A common practice for burst mode communications systems
is to differentially modulate the signal, so that a DPSK
demodulator can be used for data recovery. This form of
demodulator uses each symbol as a phase reference for the
next one. It offers rapid acquisition and tolerance to rapid
phase fluctuations at the expense of lower bit error rate
(BER) performance.
The PRISM baseband processor, HFA3824A uses differential
demodulation for the initial acquisition portion of the process-
ing and then switches to coherent demodulation for the rest of
the acquisition and data demodulation. The HFA3824A is
designed to achieve rapid settling of the carrier tracking loop
during
acquisition.
Coherent
improves the BER performance margin. Rapid phase fluctua-
tions are handled with a relatively wide loop bandwidth.
The baseband processor uses time invariant correlation to
strip the PN spreading and polar processing to demodulate
the resulting signals. These operations are illustrated in Fig-
ure 13 which is an overall block diagram of the receiver pro-
cessor. Input samples from the I and Q ADC converters are
correlated to remove the spreading sequence. The magni-
tude of the correlation pulse is used to determine the symbol
timing. The sample stream is decimated to the symbol rate
and the phase is corrected for frequency offset prior to PSK
demodulation. Phase errors from the demodulator are fed to
the NCO through a lead/lag filter to achieve phase lock. The
variance of the phase errors is used to determine signal
quality for acquisition and lock detection.
processing
substantially
HFA3824A
相关PDF资料 |
PDF描述 |
|---|---|
| HFA3824A | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3842B | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842BIN | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842BIN-TK | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842IN96 | Wireless LAN Medium Access Controller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3824AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3824AIV96 | 制造商:Rochester Electronics LLC 功能描述:BASEBAND PROCESSOR - Bulk |
| HFA3824EVAL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3824IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3824IV96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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