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参数资料
| 型号： | HFA3824AIV |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 封装： | 7 X 7 MM, PLASTIC, TQFP-48 |
| 文件页数： | 22/40页 |
| 文件大小： | 271K |
| 代理商： | HFA3824AIV |
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link is dropped and the receiver returns to the acquisition
mode. These values should typically be different for BPSK
and QPSK since the operating point in SNR differs by 3dB. If
the receiver is intended to receive both BPSK and QPSK
modulations, a compromise value must be used or the net-
work processor can control them as appropriate.
The suggested method of optimization is to set the transmit-
ter in a continuous transmit mode. Then, measure the time
until the receiver drops lock at low signal to noise ratio. Each
of the 2 thresholds should be set individually to the same
drop lock time. While setting thresholds for one of the signal
qualities the other should be configured at its limit so it does
not influence the drop lock decisions. Set CR 26 to 00h while
determining the value of CR 34 and 35 for phase error
threshold. Set CR 34 to FFh while determining the value of
CR 26 and 27 for bit sync amplitude threshold.
Assuming a 10e-6 BER operating point, it is suggested that
the drop lock thresholds are set at 10e-3 BER, with each
threshold adjusted individually.
Note that the bit sync amplitude is linearly proportional to the
signal amplitude at the ADC converters. If an AGC system is
being used instead of a limiter, the bit sync amplitude thresh-
old should be set at or below the minimum amplitude that the
radio will see at its sensitivity level.
Data Decoder and Descrambler Description
The data decoder that implements the desired DQPSK cod-
ing/decoding as shown in DQPSK Data Decoder Table 9.
This coding scheme results from differential coding of the
dibits. When used in the DBPSK modes, only the 00 and 11
dibits are used. Vector rotation is counterclockwise. Note:
the rotation sense can be reversed by CR5 <7>.
The data scrambler and de-scrambler are self synchronizing
circuits. They consist of a 7-bit shift register with feedback of
some of the taps of the register. The scrambler can be dis-
abled for measuring RF carrier suppression. The scrambler
is designed to insure smearing of the discrete spectrum lines
produced by the PN code.
One thing to keep in mind is that both the differential decod-
ing and the descrambling when used cause error extension.
This causes the errors to occur in groups of 4 and 6. This is
due to two properties of the processing. First, the differential
decoding process causes errors to occur in pairs. When a
symbol error is made, it is usually a single bit error even in
QPSK mode. When a symbol is in error, the next symbol will
also be decoded wrong since the data is encoded in the
change from one symbol to the next. Thus, two errors are
made on two successive symbols. In QPSK mode, these
may be next to one another or separated by up to 2 bits.
Secondly, when the bits are processed by the descrambler,
these errors are further extended. The descrambler is a 7-bit
shift register with one or more taps exclusive ored with the
bit stream. If for example the scrambler polynomial uses 2
taps that are summed with the data, then each error is
extended by a factor of three. Since the DPSK errors are
close together, however, some of them can be canceled in
the descrambler. In this case, two wrongs do make a right,
so the observed errors can be in groups of 4 instead of 6.
Descrambling is done by a polynomial division using a pre-
scribed polynomial. A shift register holds the last quotient
and the output is the exclusive-or of the data and the sum of
taps in the shift register. The taps and seed are programma-
ble. The transmit scrambler seed is programmed by CR 15
and the taps are set with CR 16. One reason for setting the
seed is that it can be used to make the SFD scrambling the
same every packet so that it can be recognized in its
scrambled state.
Demodulator Performance
This section indicates the theoretical performance and
typical performance measures for a radio design. The perfor-
mance data below should be used as a guide. The actual
performance depends on the application, interference
environment, RF/IF implementation and radio component
selection in general.
Overall Eb/N0 Versus BER Performance
The PRISM chip set has been designed to be robust and
energy efficient in packet mode communications. The
demodulator uses coherent processing for data demodula-
tion. Figure 17 below shows the performance of the
baseband processor when used in conjunction with the
HSP3724 IF limiter and the PRISM recommended IF filters.
Off the shelf test equipment are used for the RF processing.
The curves should be used as a guide to assess
performance in a complete implementation.
Factors for carrier phase noise, multipath, and other
degradations will need to be considered on an implementa-
tion by implementation basis in order to predict the overall
performance of each individual system.
Figure 17 shows the curve for theoretical DBPSK/DQPSK
demodulation with coherent demodulation as well as the
PRISM performance measured for DBPSK and DQPSK. The
losses include RF and IF radio losses; they do not reflect the
HFA3824A losses alone. These are more realistic measure-
ments. The HFA3824A baseband losses from theoretical by
themselves are a small percentage of the overall loss.
The PRISM demodulator performs at less than 3dB from
theoretical in a AWGN environment with low phase noise local
oscillators. The observed errors occurred in groups of 4 and 6
errors and rarely singly. This is because of the error extension
properties of differential decoding and descrambling.
TABLE 9. DQPSK DATA DECODER
PHASE SHIFT
DIBITS
0
00
+90
01
+180
11
-90
10
HFA3824A
相关PDF资料 |
PDF描述 |
|---|---|
| HFA3824A | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3842B | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842BIN | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842BIN-TK | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842IN96 | Wireless LAN Medium Access Controller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3824AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3824AIV96 | 制造商:Rochester Electronics LLC 功能描述:BASEBAND PROCESSOR - Bulk |
| HFA3824EVAL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3824IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3824IV96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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