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参数资料
| 型号： | HFA3824AIV |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 封装： | 7 X 7 MM, PLASTIC, TQFP-48 |
| 文件页数： | 33/40页 |
| 文件大小： | 271K |
| 代理商： | HFA3824AIV |
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2-131
CONFIGURATION REGISTER 37 ADDRESS (94h) RX SIGNAL QUALITY 2 DATA READ (LOW)
Bits 0-7
This register contains the lower byte bits (0-7) of the measured signal quality of the carrier phase variance. This register
combined with the represents a 16-bit value, of the measured carrier phase variance. This measurement is made every 128
symbols.
CONFIGURATION REGISTER ADDRESS 38 (98h) RX SIGNAL QUALITY 8-BIT READ
Bits 0 - 7
This 8-bit register contains the bit sync amplitude signal quality measurement derived from the 16-bit Bit Sync signal quality
value stored in the CR28-29 registers. This value is the result of the signal quality measurement for the best antenna dwell.
The signal quality measurement provides 256 levels of signal to noise measurement.
CONFIGURATION REGISTER 39 ADDRESS (9Ch) MODEM CONFIGURATION REGISTER E
Bit 7
Reserved - must set to a zero
Bit 6
Enable length field interpreted in microseconds. This bit determines if the length field in the header is treated as
microseconds or bits in the length field counter used in the CCA logic. This bit forces the counter to count at the BPSK data
rate all the time.
Logic 1 = Count at BPSK rate
Logic 0 = Count bits
Bit 5
Continuous QPSK mode. This allows the receiver to acquire on a QPSK signal (no header is required). Signal quality thresh-
olds must be satisfied. See CR4 bit 6
Logic 1 = Continuous QPSK mode
Logic 0 = Normal mode
Bit 4
Only allow Quarter chip adjustments during Data Dwells. Recommended set to a one for all modes of operation.
Logic 1 = Enabled
Logic 0 = Duplicate HSP3824 operation
Bit 3
Enable 64 symbol integrations for Data Dwells. By reducing integration time from 128 to 64 symbols, allows greater inaccu-
racies between transmitter and receiver oscillators. Thresholds must be adjusted accordingly.
Logic 1 = 64 symbol integration
Logic 0 = 128 symbol integration
Bit 2
Enable length field counter in CCA operation. This bit enables a counter which will show the channel busy for the time spec-
ified in the length field (see CR39 bit 6). The counter is only loaded if the CRC check passed. The counter is cleared by the
RESET# pin and thus will show the channel busy until the count expires, even if the modem is reset thru RX_PE or internal
means.
Logic 1 = Enable
Logic 0 = Disable
Bit 1
MD_RDY active on verify. MD_RDY pin go active to indicate completion of antenna dwell beginning of data dwell. No SFD
required. Relation of MD_RDY to RXCLK will not be guaranteed.
Logic 1 = Enable
Logic 0 = Disable
Bit 0
Reserved (must set to “0”)
CONFIGURATION REGISTER 40 ADDRESS RESERVED
Reserved
CONFIGURATION REGISTER 41 ADDRESS (A4h) SFD SEARCH TIME
Bits 0 - 7
This register is programmed with an 8-bit value which represents the length of time for the demodulator to search for a SFD
in a receive Header. Each bit increment represents 1 symbol period.
CONFIGURATION REGISTER 42 ADDRESS (A8h) DSBPSK SIGNAL
Bits 0 - 7
This registercontains an8-bit valueindicating thedatapacket modulationisDBPSK. Thisvalue will beaOAHforfull protocol
operation at a data rate of 1 MBPS, and is used in the transmitted Signalling Field of the header. This value will also be used
for detecting the modulation type on the received Header.
CONFIGURATION REGISTER 43 ADDRESS (ACh) DQPSK SIGNAL
Bits 0 - 7
This register contains the 8-bit value indicating the data packet modulation is DQPSK. This value will be a 14h for full protocol
operation at a data rate of 2 MBPS and is used in the transmitted Signalling Field of the header. This value will also be used
for detecting the modulation type on the received header.
CONFIGURATION REGISTER 44 ADDRESS (B0h) RX SERVICE FIELD (RESERVED)
Bits 0 - 7
This register contains the detected received 8-bit value of the Service Field for the Header. This field is reserved for the full
protocol mode for future use and should be always a 00h.
HFA3824A
相关PDF资料 |
PDF描述 |
|---|---|
| HFA3824A | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3842B | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842BIN | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842BIN-TK | PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842IN96 | Wireless LAN Medium Access Controller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3824AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3824AIV96 | 制造商:Rochester Electronics LLC 功能描述:BASEBAND PROCESSOR - Bulk |
| HFA3824EVAL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3824IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3824IV96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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