2-143
absolute phase reference for the data portion of the packet.
At 11MBPS, two nibbles are used, and each one is used as
above independently. One of the resulting sequences is
modulated on the I Channel and the other on the Q Channel
output. With 16 possible sequences on I and another 16
independently on Q, the total possible number of
combinations is 256. Of these only one is sent.
The bit rate Table 7 shows examples of the bit rates and the
symbol rates and Figure 8 shows the modulation schemes.
The modulator is completely independent from the
demodulator, allowing the PRISM baseband processor to be
used in full duplex operation.
Header/Packet Description
The HFA3860A is designed to handle continuous or
packetized Direct Sequence Spread Spectrum (DSSS) data
transmissions. The HFA3860A generates its own preamble
and header information.
The device uses a synchronization preamble of up to 256
symbols, and a header that includes four fields. The
preamble is all 1's plus a start frame delimiter (before
entering the scrambler). The actual transmitted pattern of
the preamble will be randomized by the scrambler. The
preamble is always transmitted as a DBPSK waveform.
Start Frame Delimiter (SFD) Field (16 Bits)
This carries the synchronization to establish the link frame
timing. The HFA3860A will not declare a valid data packet,
even if it PN acquires, unless it detects the SFD. The
HFA3860A receiver is programmed to time out searching for
the SFD via CR15. The timer starts counting the moment
that initial PN synchronization has been established from the
preamble.
TABLE 7. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz
DATA
MODULATION
A/D SAMPLE CLOCK
(MHZ)
TX SETUP CR 20
BITS 1, 0
RX STATUS CR 24
BITS 7, 6
DATA RATE
(MBPS)
SYMBOL RATE
(MSPS)
DBPSK
22
00
00
1
1
DQPSK
22
01
01
2
1
BMBOK
22
10
10
5.5
1.375
QMBOK
22
11
11
11
1.375
802.11 DSSS BPSK
1 MB/S
BARKER
802.11 DSSS QPSK
2 MB/S
BARKER
5.5 MB/S BMBOK
MODIFIED
WALSH FUNCTIONS
11 MB/S QMBOK
MODIFIED
WALSH FUNCTIONS
DATA
IOUT
QOUT
CHIP
RATE
1 BIT ENCODED TO ONE OF
2 CODE WORDS
(TRUE/INVERSE)
2 BITS ENCODED
TO ONE OF
4 CODE WORDS
4 BITS ENCODED TO ONE OF
16 MODIFIED WALSH
CODE WORDS
8 BITS ENCODED TO
ONE OF
256 MODIFIED WALSH
CODE WORDS
SYMBOL
RATE
I vs Q
11 MC/S
11 MC/S
11 MC/S
11 MC/S
1 MS/S
1 MS/S
1.375 MS/S
1.375 MS/S
11 CHIPS
11 CHIPS
8 CHIPS
8 CHIPS
FIGURE 8. MODULATION MODES
HFA3860A