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参数资料
| 型号： | HFA3860AIV |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | 3.3V 288-mc CPLD |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 封装： | 7 X 7 X 1 MM, PLASTIC, TQFP-48 |
| 文件页数： | 20/39页 |
| 文件大小： | 251K |
| 代理商： | HFA3860AIV |
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2-150
The Walsh correlation section consists of a bank of 8 serial
correlators on I and 8 on Q. Each of these correlators is
programmed to correlate for its assigned spread function or its
inverse. The demodulator knows the symbol timing, so the
correlation is integrated over each symbol and sampled and
dumped at the end of the symbol. The sampled correlation
outputs from each bank are compared to each other in a
biggest picker and the chosen one determines 4 bits of the
symbol. Three bits come from which of the 8 correlators had
the largest output and the fourth is determined from the sign of
that output. In the 5.5MBPS or binary mode, only the I Channel
is operated. This demodulates 4 bits per symbol. In the
11MBPS mode, both I and Q Channels are used and this
detects 8 bits per symbol. The outputs are corrected for
absolute phase and then serialized for the descrambler.
Chip tracking is performed on the de-rotated signal samples
from the complex multiplier. These are alternately routed into
two streams. The END chip samples are the same as those
used for the correlators. The MID chip samples should lie on
the chip transitions when the tracking is perfect. A chip phase
error is generated if the END sign bits bracketing the MID
samples are different. The sign of the error is determined by
the sign of the END sample after the MID sample.
Tracking is only measured when there is a chip transition.
Note that this tracking is mainly effective since there is a
positive SNR in the chip rate bandwidth.
The symbol clock is generated by selecting one 44 MHz clock
pulse out of every 32 pulses of the sample clock. Chip tracking
adjusts the sampling in 1/8th chip increments by selecting
which edge of the 44 MHz clock to use and which pulse. Timing
adjustments can be made every 32 symbols as needed.
Carrier tracking is performed in a four phase Costas loop. The
initial conditions are copied into the loop from the carrier loop
in the low rate section. The END samples from above are
used for the phase detection. The phase error for the 11MBps
case is derived from Isign*Q-Qsign*I whereas in binary mode,
it is simply Isign*Q. This forms the error term that is integrated
in the lead/lag filter for the NCO, closing the loop.
HFA3860A
相关PDF资料 |
PDF描述 |
|---|---|
| HFA3861AIN96 | Circular Connector; No. of Contacts:21; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:22-21 RoHS Compliant: No |
| HFA3861AIN | 288 MACROCELL 3.3 VOLT ISP CPLD |
| HFA3863IN | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863 | Direct Sequence Spread Spectrum Baseband Processor(直接序列扩谱基带处理器) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3860AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860AIV96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:nullDirect Sequence Spread Spectrum Baseband Processor |
| HFA3860BIV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860BIV WAF | 制造商:Harris Corporation 功能描述: |
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