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参数资料
| 型号： | HFA3860AIV |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | 3.3V 288-mc CPLD |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 封装： | 7 X 7 X 1 MM, PLASTIC, TQFP-48 |
| 文件页数： | 19/39页 |
| 文件大小： | 251K |
| 代理商： | HFA3860AIV |
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sampled at the symbol rate of 1.375MSPS. Each bank of
correlators is connected to a biggest picker that finds the
correlator output with the largest magnitude output. This finding
of 1 out of 8 process determines 3 signal bits per correlator
bank. The sign of the correlator output determines 1 more bit
per bank. Thus, each bank of correlators can determine 4 bits
at 1.375MSPS. This is a rate of 5.5MBPS. Only the I correlator
bank is used for BMBOK. When both correlator banks are
used, this becomes twice that rate or 11MBPS.
Data Demodulation and Tracking
Description (DBPSK and DQPSK Modes)
The signal is demodulated from the correlation peaks tracked
by the symbol timing loop (bit sync) as shown in Figure 14.
The frequency and phase of the signal is corrected from the
NCO that is driven by the phase locked loop. Demodulation of
the DPSK data in the early stages of acquisition is done by
delay and subtraction of the phase samples. Once phase
locked loop tracking of the carrier is established, coherent
demodulation is enabled for better performance. Averaging
the phase errors over 16 symbols gives the necessary
frequency information for proper NCO operation. The signal
quality known as SQ2 is the variance in this estimate.
Configuration Register 15 sets the search timer for the SFD.
This register sets this time-out length in symbols for the
receiver. If the time out is reached, and no SFD is found, the
receiver resets to the acquisition mode. The suggested value
is # preamble symbols + 16. If several transmit preamble
lengths are used by various transmitters in a network, the
longest value should be used for the receiver settings.
Data Decoder and Descrambler Description
The data decoder that implements the desired DQPSK
coding/decoding as shown in Table 10. The data is formed
into pairs of bits called dibits. The left bit of the pair is the first
in time. This coding scheme results from differential coding
of the dibits. Vector rotation is counterclockwise for a positive
phase shift, but can be reversed with bit 5 or 6 of CR2.
For DBPSK, the decoding is simple differential decoding.
The data scrambler and descrambler are self synchronizing
circuits. They consist of a 7-bit shift register with feedback of
some of the taps of the register. The scrambler is designed
to insure smearing of the discrete spectrum lines produced
by the PN code.
One thing to keep in mind is that both the differential decoding
and the descrambling cause error extension. This causes the
errors to occur in groups of 4 and 6. This is due to two
properties of the processing. First, the differential decoding
process causes errors to occur in pairs. When a symbol error is
made, it is usually a single bit error even in QPSK mode. When
asymbolisinerror,thenextsymbolwillalsobedecodedwrong
since the data is encoded in the change from one symbol to the
next. Thus, two errors are made on two successive symbols. In
QPSK mode, these may be next to one another or separated
by up to 2 bits. Secondly, when the bits are processed by the
descrambler, these errors are further extended. The
descrambler is a 7-bit shift register with one or more taps
exclusive or’ed with the bit stream. If for example the scrambler
polynomial uses 2 taps that are summed with the data, then
each error is extended by a factor of three. DQPSK errors can
be spaced the same as the tap spacing, so they can be
canceled in the descrambler. In this case, two wrongs do make
a right, so the observed errors can be in groups of 4 instead of
6. If a single error is made the whole packet is discarded, so the
error extension property has no effect on the packet error rate.
Descrambling is self synchronizing and is done by a
polynomial division using a prescribed polynomial. A shift
register holds the last quotient and the output is the exclusive-
or of the data and the sum of taps in the shift register. The
transmit scrambler taps are programmed by CR 7.
Data Demodulation and Tracking
Description (BMBOK and QMBOK Modes)
This demodulator handles the M-ary Bi-Orthogonal Keying
(MBOK) modulation used for the two highest data rates. It is
slaved to the low rate processor which it depends on for initial
timing and phase tracking information. The high rate section
coherently processes the signal, so it needs to have the I and Q
Channels properly oriented and phased. The low rate section
acquires the signal, locks up symbol and carrier tracking loops,
and determines the data rate to be used for the MPDU data.
The demodulator for the MBOK modes takes over when the
preamble and header have been acquired and processed. On
the last bit of the header, the absolute phase of the signal is
captured and used as a phase reference for the high rate
demodulator as shown in Figure 15. The phase and
frequency information from the carrier tracking loop in the low
rate section is passed to the loop of the high rate section and
control of the demodulator is passed to the high rate section.
The signal from the A/D converters is carrier frequency and
phase corrected by a complex multiplier (mixer) that multiplies
the received signal with the output of the Numerically
Controlled Oscillator (NCO) and SIN/COS look up table. This
removes the frequency offset and aligns the I and Q Channels
properly for the correlators. The sample rate is decimated to
11MSPS for the correlators after the complex multiplier since
the data is now synchronous in time.
TABLE 10. DQPSK DATA DECODER
PHASE SHIFT
DIBIT PATTERN (D0, D1)
D0 IS FIRST IN TIME
0
00
+90
01
+180
11
-90
10
HFA3860A
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| HFA3861AIN | 288 MACROCELL 3.3 VOLT ISP CPLD |
| HFA3863IN | Direct Sequence Spread Spectrum Baseband Processor |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3860AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860AIV96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:nullDirect Sequence Spread Spectrum Baseband Processor |
| HFA3860BIV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860BIV WAF | 制造商:Harris Corporation 功能描述: |
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