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参数资料
| 型号： | HFA3860AIV |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | 3.3V 288-mc CPLD |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 封装： | 7 X 7 X 1 MM, PLASTIC, TQFP-48 |
| 文件页数： | 5/39页 |
| 文件大小： | 251K |
| 代理商： | HFA3860AIV |
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2-135
TXD
3
I
TXD is an input, used to transfer MAC Payload Data Unit (MPDU) data from the MAC or network
processor to the HFA3860A. The data is received serially with the LSB first. The data is clocked in the
HFA3860A at the rising edge of TXCLK.
TXCLK
4
O
TXCLK is a clock output used to receive the data on the TXD from the MAC or network processor to
the HFA3860A, synchronously. Transmit data on the TXD bus is clocked into the HFA3860A on the
rising edge. The clocking edge is also programmable to be on either phase of the clock. The rate of the
clock will be dependent upon the data rate that is programmed in the signalling field of the header.
TX_RDY
5
O
TX_RDY is an output to the external network processor indicating that Preamble and Header
information has been generated and that the HFA3860A is ready to receive the data packet from the
network processor over the TXD serial bus. The TX_RDY returns to the inactive state when the last chip
of the last symbol has been output.
CCA
32
O
Clear Channel Assessment (CCA) is an output used to signal that the channel is clear to transmit. The
CCA algorithm makes its decision as a function of RSSI, Energy detect (ED), and Carrier Sense (CRS).
The CCA algorithm and its features are described elsewhere in the data sheet.
Logic 0 = Channel is clear to transmit.
Logic 1 = Channel is NOT clear to transmit (busy).
This polarity is programmable and can be inverted.
RXD
35
O
RXD is an output to the external network processor transferring demodulated Header information and
data in a serial format. The data is sent serially with the LSB first. The data is frame aligned with MD_RDY.
RXCLK
36
O
RXCLK is the bit clock output. This clock is used to transfer Header information and payload data through
the RXD serial bus to the network processor. This clock reflects the bit rate in use. RXCLK is held to a
logic “0” state during the CRC16 reception. RXCLK becomes active after the SFD has been detected.
Data should be sampled on the rising edge. This polarity is programmable and can be inverted.
MD_RDY
34
O
MD_RDY is an output signal to the network processor, indicating header data and a data packet are
ready to be transferred to the processor. MD_RDY is an active high signal and it envelopes the data
transfer over the RXD serial bus. MD_RDY goes active when the SFD is detected and returns to its
inactive state when RX_PE goes inactive or an error is detected in the header.
RX_PE
33
I
When active, the receiver is configured to be operational, otherwise the receiver is in standby mode.
This is an active high input signal. In standby, RX_PE inactive, all A/D converters are disabled.
SD
25
I/O
SD is a serial bidirectional data bus which is used to transfer address and data to/from the internal registers.
The bit ordering of an 8-bit word is MSB first. The first 8 bits during transfers indicate the register address
immediately followed by 8 more bits representing the data that needs to be written or read at that register.
SCLK
24
I
SCLK is the clock for the SD serial bus. The data on SD is clocked at the rising edge. SCLK is an input
clock and it is asynchronous to the internal master clock (MCLK). The maximum rate of this clock is
11MHz or one half the master clock frequency, whichever is lower.
SDI
23
I
Serial Data Input in 3 wire mode described in Tech Brief 362. This pin is not used in the 4 wire interface
described in this data sheet. It should not be left floating.
R/W
8
I
R/W is an input to the HFA3860A used to change the direction of the SD bus when reading or writing
data on the SD bus. R/W also enables the serial shift register used in a read cycle. R/W must be set up
prior to the rising edge of SCLK. A high level indicates read while a low level is a write.
CS
9
I
CS is a Chip Select for the device to activate the serial control port. The CS doesn’t impact any of the
other interface ports and signals, i.e., the TX or RX ports and interface signals. This is an active low
signal. When inactive SD, SCLK, and R/W become “don’t care” signals.
TEST 7:0
37, 38, 39,
40, 43, 44,
45, 46
O
This is a data port that can be programmed to bring out internal signals or data for monitoring. These
bits are primarily reserved by the manufacturer for testing. A further description of the test port is given
at the appropriate section of this data sheet.
TEST_CK
1
O
This is the clock that is used in conjunction with the data that is being output from the test bus (TEST 0-7).
RESET
28
I
Master reset for device. When active TX and RX functions are disabled. If RESET is kept low the
HFA3860A goes into the power standby mode. RESET does not alter any of the configuration register
values nor does it preset any of the registers into default values. Device requires programming upon
power-up.
MCLK
30
I
Master Clock for device. The nominal frequency of this clock is 44MHz. This is used internally to gen-
erate all other internal necessary clocks and is divided by 2 or 4 for the transceiver clocks.
I
OUT
Q
OUT
48
O
TX Spread baseband I digital output data. Data is output at the chip rate.
47
O
TX Spread baseband Q digital output data. Data is output at the chip rate.
NOTE: Total of 48 pins; ALL pins are used.
Pin Descriptions
(Continued)
NAME
PIN
TYPE I/O
DESCRIPTION
HFA3860A
相关PDF资料 |
PDF描述 |
|---|---|
| HFA3861AIN96 | Circular Connector; No. of Contacts:21; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:22-21 RoHS Compliant: No |
| HFA3861AIN | 288 MACROCELL 3.3 VOLT ISP CPLD |
| HFA3863IN | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863 | Direct Sequence Spread Spectrum Baseband Processor(直接序列扩谱基带处理器) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3860AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860AIV96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:nullDirect Sequence Spread Spectrum Baseband Processor |
| HFA3860BIV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860BIV WAF | 制造商:Harris Corporation 功能描述: |
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