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参数资料
型号： HW-V5-ML555-G
厂商： Xilinx Inc
文件页数： 4/108页
文件大小： 0K
描述： BOARD EVAL FOR VIRTEX-5 ML555
产品培训模块： PCI Express and Virtex® -5 FPGAs
标准包装： 1
系列： Virtex® -5
类型： FPGA
适用于相关产品： Virtex?-5 FPGA
所含物品： 板，线缆，CD
配用： HW-AFX-SMA-SFP-ND - CONVERSION MODULE SMA - SFP
HW-AFX-SMA-SATA-ND - CONVERSION MODULE SMA - SATA
HW-AFX-SMA-RJ45-ND - CONVERSION MODULE SMA - RJ45
HW-AFX-SMA-HSSDC2-ND - CONVERSION MODULE SMA - HSSDC2
HW-AFX-BERG-EPHY-ND - DAUGHTER CARD PHY BERG-EPHY
相关产品： XC5VFX70T-1FF1136CES-ND - IC FPGAVIRTEX5FX ES 70K 1136FBGA
XC5VLX85T-3FF1136C-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX85T-2FF1136I-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX85T-2FF1136C-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX85T-1FF1136I-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX85T-1FF1136C-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX50T-3FF1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FF1136I-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FF1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-1FF1136I-ND - IC FPGA VIRTEX-5 50K 1136FBGA
更多...
其它名称： 122-1586
HW-V5-ML555-G-ND
Date
03/10/08
Version
1.4
Revision
Added additional reference documents and application notes in “Additional
Documentation,” page 7 . Added link to ML555 website in “About the Virtex-5 FPGA
ML555 Development Kit,” page 13 . Updated “Serial Bus Development,” page 15 ,
including removal of Virtex-5 LogiCORE Endpoint Block Wrapper. Included Platform
USB Programming Cable and ISE Evaluation Software in “Kit Contents,” page 15 .
Specified 30 MHz LVCMOS oscillator as one of three on board clock sources in “ML555
Board,” page 15 . Updated Figure 3-1, page 21 to reflect “as built” 30 MHz LVCMOS
oscillator. Added reference and link to Xilinx application notes XAPP1022 and
XAPP1002 in “Edge Connector for PCI Express Operation,” page 23 . Added footnote 6
to Table 3-1, page 24 to identify FPGA connection of PCIE_PERST. Added PCIE_PERST
to Table 3-3, page 27 . Added reference and link to XAPP999 in “Reference Designs for
PCI and PCI-X Operation,” page 33 . Added reference and links to Xilinx application
notes XAPP858 and XAPP865 in “DDR2 SDRAM SODIMM,” page 34 . Corrected FPGA
pin assignments for IIC_SDA_SFP{1/2} and IIC_SCK_SFP{1/2} signals and updated
footnotes 2 and 5 in Table 3-7, page 39 . Added reference and link to application note
XAPP870 in “Serial ATA Interface,” page 40 . Corrected FPGA pin assignment for
P1_RCLK1 signal in Table 3-11, page 43 . Added website link to download Silicon
Laboratories VCP device drivers in the “USB to UART Bridge,” page 51 . Specify 30 MHz
oscillator frequency for component Y2 in Table 3-18, page 53 . Changed signal name for
FPGA GCLK input pin L19 to FPGA_GCLK_30MHZ in Figure 3-8, page 55 , Figure 3-9,
page 56 , and Table 3-19, page 57 . Changed signal name for FPGA GCLK input pin AD32
to FPGA_GCLK_30MHZ in Table 3-26, page 70 . Added footnote to Table 3-37, page 86 .
Updated footnote 3 in Table 4-1, page 89 to recommend Master SelectMAP configuration
of the ML555. Changed CPLD CLK to 30 MHz in Figure 4-5, page 92 , Figure 4-6, page 98 ,
and Figure 4-7, page 99 as well as Table 4-4, page 94 . Changed oscillator Y2 frequency to
30 MHz in Figure 4-8, page 100 . Added footnote to Table 4-7, page 100 concerning CCLK
configuration frequency recommendation. Added BitGen command sequence to
demonstrate selection of 20 MHz CCLK configuration clock in “Platform Flash Image
Generation and Programming,” page 101 .
Virtex-5 FPGA ML555 Development Kit
www.xilinx.com
UG201 (v1.4) March 10, 2008
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