参数资料
型号: HW-V5-ML555-G
厂商: Xilinx Inc
文件页数: 47/108页
文件大小: 0K
描述: BOARD EVAL FOR VIRTEX-5 ML555
产品培训模块: PCI Express and Virtex® -5 FPGAs
标准包装: 1
系列: Virtex® -5
类型: FPGA
适用于相关产品: Virtex?-5 FPGA
所含物品: 板,线缆,CD
配用: HW-AFX-SMA-SFP-ND - CONVERSION MODULE SMA - SFP
HW-AFX-SMA-SATA-ND - CONVERSION MODULE SMA - SATA
HW-AFX-SMA-RJ45-ND - CONVERSION MODULE SMA - RJ45
HW-AFX-SMA-HSSDC2-ND - CONVERSION MODULE SMA - HSSDC2
HW-AFX-BERG-EPHY-ND - DAUGHTER CARD PHY BERG-EPHY
相关产品: XC5VFX70T-1FF1136CES-ND - IC FPGAVIRTEX5FX ES 70K 1136FBGA
XC5VLX85T-3FF1136C-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX85T-2FF1136I-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX85T-2FF1136C-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX85T-1FF1136I-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX85T-1FF1136C-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX50T-3FF1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FF1136I-ND - IC FPGA VIRTEX-5 50K 1136FBGA
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XC5VLX50T-1FF1136I-ND - IC FPGA VIRTEX-5 50K 1136FBGA
更多...
其它名称: 122-1586
HW-V5-ML555-G-ND
R
Table 3-12:
SAMTEC Pin Connections (P32) (Continued)
LVDS Interface
SAMTEC-QSE-
028-DP P32
Odd
73
75
77
79
Signal (1)
No connect
GND
GPIO1_I22_N (2)
GPIO1_I22_P (2)
FPGA
Pin
N/A
N/A
K12
K13
SAMTEC-QSE-
028-DP P32
Even
74
76
78
80
Signal (1)
No connect
GND
GPIO1_I23_N (2)
GPIO1_I23_P (2)
FPGA
Pin
N/A
N/A
H12
J12
Notes:
1. These signals are connected to FPGA banks 1 and 19. The FPGA reference voltage for these banks is
2.5V. See the ML555 board schematics on the CD-ROM for additional information.
2. Bank 1 GPIO clock-capable I/O signals. All others are in FPGA Bank 19.
3. NC = no connect.
4. Bank 19 clock-capable I/O pins.
Table 3-13:
SAMTEC Pin Connections (P33)
SAMTEC-QSE-
028-DP P33
Odd
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
Signal (1)
GP1O2_I23_P (2)
GP1O2_I23_N (2)
GND
No Connect
No Connect
GND
GP1O2_I21_P
GP1O2_I21_N
GND
GP1O2_I19_P
GP1O2_I19_N
GND
GP1O2_I17_P
GP1O2_I17_N
GND
GP1O2_I15_P
GP1O2_I15_N
GND
GP1O2_I13_P (4)
FPGA
Pin
AF13
AG12
N/A
N/A
N/A
N/A
AC4
AC5
N/A
AA5
AB5
N/A
Y8
Y9
N/A
AA6
Y7
N/A
W6
SAMTEC-QSE-
028-DP P33
Even
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
Signal (1)
GP1O2_I22_P (2)
GP1O2_I22_N (2)
GND
No Connect
No Connect
GND
GP1O2_I20_P
GP1O2_I20_N
GND
GP1O2_I18_P
GP1O2_I18_N
GND
GP1O2_I16_P
GP1O2_I16_N
GND
GP1O2_I14_P
GP1O2_I14_N
GND
GP1O2_I12_P (4)
FPGA
Pin
AE13
AE12
N/A
N/A
N/A
N/A
AB6
AB7
N/A
AC7
AD7
N/A
AD4
AD5
N/A
AD6
AE6
N/A
AE7
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
47
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