参数资料
型号: HW-V5-ML555-G
厂商: Xilinx Inc
文件页数: 66/108页
文件大小: 0K
描述: BOARD EVAL FOR VIRTEX-5 ML555
产品培训模块: PCI Express and Virtex® -5 FPGAs
标准包装: 1
系列: Virtex® -5
类型: FPGA
适用于相关产品: Virtex?-5 FPGA
所含物品: 板,线缆,CD
配用: HW-AFX-SMA-SFP-ND - CONVERSION MODULE SMA - SFP
HW-AFX-SMA-SATA-ND - CONVERSION MODULE SMA - SATA
HW-AFX-SMA-RJ45-ND - CONVERSION MODULE SMA - RJ45
HW-AFX-SMA-HSSDC2-ND - CONVERSION MODULE SMA - HSSDC2
HW-AFX-BERG-EPHY-ND - DAUGHTER CARD PHY BERG-EPHY
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XC5VLX85T-2FF1136I-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX85T-2FF1136C-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX85T-1FF1136I-ND - IC FPGA VIRTEX-5 85K 1136FBGA
XC5VLX85T-1FF1136C-ND - IC FPGA VIRTEX-5 85K 1136FBGA
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XC5VLX50T-2FF1136I-ND - IC FPGA VIRTEX-5 50K 1136FBGA
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XC5VLX50T-1FF1136I-ND - IC FPGA VIRTEX-5 50K 1136FBGA
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其它名称: 122-1586
HW-V5-ML555-G-ND
Chapter 3: Hardware Description
R
Table 3-23 shows the clock synthesis ranges possible with different selections of multiplier
M and divisor N inputs to the ICS8442 device with a 25 MHz reference clock input for
Clock Synthesizer 2.
Table 3-23:
Clock Synthesizer 2 Frequency Output for Multiplier/Divider Values with a 25 MHz Input Clock
Multiplier Input
Selection
(hex)
M8 M[7:0]
VCO Lock Output Frequency
Frequency Range (MHz) with Divisor =
(MHz) 1 N[1:0]=00b
Output
Frequency (MHz)
with Divisor = 2
N[1:0]=01b
Output
Frequency
(MHz) with
Divisor = 4
N[1:0]=10b
Output
Frequency
(MHz) with
Divisor = 8
N[1:0]=11b
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0x00 – 0x09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
0x1D – 0xFF
0x00 – 0xFF
Will not LOCK
250
275
300
325
350
375
400
425
450
475
500
525
550
575
600
625
650
675
700
Will not LOCK
N/A
250
275
300
325
350
375
400
425
450
475
500
525
550
575
600
625
650
675
700
N/A
N/A
125
137.5
150
162.5
175
187.5
200
212.5
225
237.5
250
262.5
275
287.5
300
312.5
325
337.5
350
N/A
N/A
62.5
68.75
75
81.25
87.5
93.75
100
106.25
112.5
118.75
125
131.25
137.5
143.75
150
156.25
162.5
168.75
175
N/A
N/A
31.25
34.375
37.5
40.625
43.75
46.875
50
53.125
56.25
59.375
62.5
65.625
68.75
71.875
75
78.125
81.25
84.375
87.5
N/A
66
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
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