- 您现在的位置：买卖IC网 > PDF目录384468 > HY5PS1G821M (Hynix Semiconductor Inc.) 1Gb DDR2 SDRAM(DDP) PDF资料下载
参数资料
| 型号： | HY5PS1G821M |
| 厂商： | Hynix Semiconductor Inc. |
| 英文描述： | 1Gb DDR2 SDRAM(DDP) |
| 中文描述： | 1G DDR2内存（铂） |
| 文件页数： | 26/79页 |
| 文件大小： | 1109K |
| 代理商： | HY5PS1G821M |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页当前第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页
Rev. 0.2 / Oct. 2005
26
1
HY5PS12421(L)M
HY5PS12821(L)M
2.5 Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS
high, CS and CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether
the access cycle is a read operation (WE high) or a write operation (WE low).
The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a
serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted
to specific segments of the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of
2048 bits (defined by CA0-CA9, CA11). The page length of 2048 is divided into 512 or 256 uniquely addres-
sable boundary segments depending on burst length, 512 for 4 bit burst, 256 for 8 bit burst respectively. A 4-
bit or 8 bit burst operation will occur entirely within one of the 512 or 256 groups beginning with the column
address supplied to the device during the Read or Write Command (CA0-CA9, CA11). The second, third and
fourth access will also occur within this group segment, however, the burst order is a function of the starting
address, and the burst sequence.
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However,
in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by
a read, the other writes interrupted by a write with 4 bit burst boundry respectively
.
The minimum CAS to
CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles.
相关PDF资料 |
PDF描述 |
|---|---|
| HY5PS1G821M-C4 | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821M-E3 | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421LM | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421LM-C4 | 1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421LM-E3 | 1Gb DDR2 SDRAM(DDP) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5PS1G821M-C4 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821M-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G831AFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831AFP-C4 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831ALFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
发布紧急采购，3分钟左右您将得到回复。