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| 型号： | HY5R256HC |
| 英文描述： | -|2.5V|8K|40|Direct RDRAM - 256M |
| 中文描述： | - |为2.5V | 8K的| 40 |直接RDRAM的- 256M |
| 文件页数： | 13/64页 |
| 文件大小： | 4542K |
| 代理商： | HY5R256HC |
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Rev.0.9 / Dec.2000
13
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
ROW-to-ROW Interaction - contin-
ued
Cases RR13 through RR16 summarize the combinations of
two successive PRER commands. In case RR13 there is no
restriction since two devices are addressed. In RR14, t
PP
applies, since the same device is addressed. In RR15 and
RR16, the same bank or an adjacent bank may be given
repeated PRER commands with only the t
PP
restriction.
Two adjacent banks can’t be activate simultaneously. A
precharge command to one bank will thus affect the state of
the adjacent banks (and sense amps). If bank Ba is activate
and a PRER is directed to Ba, then bank Ba will be
precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If
bank Ba+1 is activate and a PRER is directed to Ba, then
bank Ba+1 will be precharged along with sense amps
Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a
PRER is directed to Ba, then bank Ba-1 will be precharged
along with sense amps Ba/Ba-1 and Ba-1/Ba-2.
A ROW packet may contain commands other than ACT or
PRER. The REFA and REFP commands are equivalent to
ACT and PRER for interaction analysis purposes. The inter-
action rules of the NAPR, NAPRC, PDNR, RLXR, ATTN,
TCAL, and TCEN commands are discussed in later sections
(see Table 6 for cross-ref).
ROW-to-COL Packet Interaction
Figure 7: shows two packets on the ROW and COL pins.
They must be separated by an interval t
RCDELAY
which
depends upon the packet contents. Table 10 summarizes the
t
RCDELAY
values for all possible cases. Note that if the COL
packet is earlier than the ROW packet, it is considered a
COL-to-ROW packet interaction.
Cases RC1 through RC5 summarize the rules when the
ROW packet has an ACT command. Figure 15: and Figure
16: show examples of RC5 - an activation followed by a
read or write. RC4 is an illegal situation, since a read or
write of a precharged banks is being attempted (remember
that for a bank to be activated, adjacent banks must be
precharged). In cases RC1, RC2, and RC3, there is no inter-
action of the ROW and COL packets.
Cases RC6 through RC8 summarize the rules when the
ROW packet has a PRER command. There is either no inter-
action (RC6 through RC9) or an illegal situation with a read
or write of a precharged bank (RC9).
The COL pins can also schedule a precharge operation with
a RDA, WRA, or PREC command in a COLC packet or a
PREX command in a COLX packet. The constraints of these
precharge operations may be converted to equivalent PRER
command constraints using the rules summarized in Figure
14:.
Figure 7: ROW-to-COL Packet Interaction- Timing
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
T
17
T
18
T
19
Transaction a: ROPa
Transaction b: COPb
a0 = {Da,Ba,Ra}
b1= {Db,Bb,Cb1}
t
RCDELAY
ROPa a0
COPb b1
Table 10: ROW-to-COL Packet Interaction - Rules
Case #
ROPa
Da
Ba
Ra
COPb
Db
Bb
Cb1
t
RCDELAY
Example
RC1
ACT
Da
Ba
Ra
NOCOP,RD,WR
/= Da
xxxx
x..x
0
RC2
ACT
Da
Ba
Ra
NOCOP
== Da
xxxx
x..x
0
RC3
ACT
Da
Ba
Ra
RD,WR
== Da
/= {Ba,Ba+1,Ba-1}
x..x
0
RC4
ACT
Da
Ba
Ra
RD,WR
== Da
== {Ba+1,Ba-1}
x..x
Illegal
RC5
ACT
Da
Ba
Ra
RD,WR
== Da
== Ba
x..x
t
RCD
Figure 15:
RC6
PRER
Da
Ba
Ra
NOCOP,RD,WR
/= Da
xxxx
x..x
0
RC7
PRER
Da
Ba
Ra
NOCOP
== Da
xxxx
x..x
0
RC8
PRER
Da
Ba
Ra
RD,WR
== Da
/= {Ba,Ba+1,Ba-1}
x..x
0
RC9
PRER
Da
Ba
Ra
RD,WR
== Da
== {Ba+1,Ba-1}
x..x
Illegal
相关PDF资料 |
PDF描述 |
|---|---|
| HY5R288HC | -|2.5V|8K|40|Direct RDRAM - 288M |
| HY5V16CF | 1Mx16|3.3V|4K|H|SDR SDRAM - 16M |
| HY5V16CF-H | x16 SDRAM |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5S2B6DLF-BE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S2B6DLFP-BE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S2B6DLFP-SE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S2B6DLF-SE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S5B2BLF-6E | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M (8Mx32bit) Mobile SDRAM |
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