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| 型号： | HY5R256HC |
| 英文描述： | -|2.5V|8K|40|Direct RDRAM - 256M |
| 中文描述： | - |为2.5V | 8K的| 40 |直接RDRAM的- 256M |
| 文件页数： | 17/64页 |
| 文件大小： | 4542K |
| 代理商： | HY5R256HC |
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Rev.0.9 / Dec.2000
17
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
Figure 12: shows examples of the PRER-to-PRER (RR13,
RR14) and PRER-to-ACT (RR9, RR10) command spacings
from Table 9. The RR15 and RR16 cases (PRER-to-PRER
to same or adjacent banks) are not shown, but are similar to
RR14. In general, the commands in ROW packets may be
spaced an interval t
PACKET
apart unless they are directed to
the same or adjacent banks or unless they are a similar
command type (both PRER or both ACT) directed to the
same device.
Row and Column Cycle Description
Activate:
A row cycle begins with the activate (ACT) opera-
tion. The activation process is destructive; the act of sensing
the value of a bit in a bank’s storage cell transfers the bit to
the sense amp, but leaves the original bit in the storage cell
with an incorrect value.
Restore:
Because the activation process is destructive, a
hidden operation called restore is automatically performed.
The restore operation rewrites the bits in the sense amp back
into the storage cells of the activated row of the bank.
Read/Write:
While the restore operation takes place, the
sense amp may be read (RD) and written (WR) using
column operations. If new data is written into the sense amp,
it is automatically forwarded to the storage cells of the bank
so the data in the activated row and the data in the sense amp
remain identical.
Precharge:
When both the restore operation and the column
operations are completed, the sense amp and bank are
precharged (PRE). This leaves them in the proper state to
begin another activate operation.
Intervals:
The activate operation requires the interval
t
RCD,MIN
to complete. The hidden restore operation requires
the interval t
RAS,MIN
- t
RCD,MIN
to complete. Column read
and write operations are also performed during the t
RAS,MIN
- t
RCD,MIN
interval (if more than about four column opera-
tions are performed, this interval must be increased). The
precharge operation requires the interval t
RP,MIN
to
complete.
Adjacent Banks:
An RDRAM with a “s” designation
(512Kx32sx16/18) indicates it contains “split banks”. This
means the sense amps are shared between two adjacent
banks. The only exception is that sense amp 0, 15, 16, and
31 are not shared. When a row in a bank is activated, the two
adjacent sense amps are connected to (associated with) that
bank and are not available for use by the two adjacent banks.
These two adjacent banks must remain precharged while the
selected bank goes through its activate, restore, read/write,
and precharge operations.
For example (referring to the block diagram of Figure 2:), if
bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will
both be loaded with one of the 512 rows (with 512 bytes
loaded into each sense amp from the 2Kbyte row - 512 bytes
to the DQA side and 512 bytes to the DQB side). While this
row from bank 5 is being accessed, no rows may be accessed
in banks 4 or 6 because of the sense amp sharing.
Figure 12: Row Packet Examples
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
PRER a0
ACT b0
t
PACKET
PRER c0
a0 = {Da,Ba,Ra}
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
c0 = {Da,Ba,Rc}
Different Device
Same Device
Same Device
Any Bank
Non-adjacent Bank
Adjacent Bank
RR13
RR14
RR15
PRER a0
PRER a0
PRER b0
ACT c0
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
Different Device
Same Device
Any Bank
Non-adjacent Bank
RR9
RR10
PRER a0
c0 = {Da,Ba+1Rc}
Same Device
Same Bank
RR16
t
PP
t
PACKET
t
PACKET
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| HY5V16CF | 1Mx16|3.3V|4K|H|SDR SDRAM - 16M |
| HY5V16CF-H | x16 SDRAM |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5S2B6DLF-BE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S2B6DLFP-BE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S2B6DLFP-SE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S2B6DLF-SE | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S5B2BLF-6E | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M (8Mx32bit) Mobile SDRAM |
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