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参数资料
| 型号： | HYS72T256300EP-3.7-C |
| 厂商： | QIMONDA AG |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封装： | GREEN, RDIMM-240 |
| 文件页数： | 20/41页 |
| 文件大小： | 2780K |
| 代理商： | HYS72T256300EP-3.7-C |
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HYS72T256300EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
Internet Data Sheet
Rev. 1.0, 2007-07
27
07312007-34WH-CYDW
3.3.3
ODT AC Electrical Characteristics
This chapter describes the ODT AC electrical characteristics.
TABLE 17
ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800
12) MIN (
t
CL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for
t
CL and tCH).
13) The
t
HZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(
t
HZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85
°C
and 95
°C.
15) 0 °C
≤ T
CASE ≤ 85 °C
16) 85
°C < T
CASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The
t
RRD timing parameter depends on the page size of the DRAM organization.
19) The maximum limit for the
t
WPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum
t
WTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing
t
XARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing
t
XARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the
t
WR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value.
t
DAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
t
AOND
ODT turn-on delay
2
n
CK
1)
1) New units, “tCK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800. Unit “tCK.AVG” represents the actual tCK.AVG of the input clock
under operation. Unit “
n
CK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “
t
CK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at
T
m + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min).
t
AON
ODT turn-on
t
AC.MIN
t
AC.MAX +0.7 ns
ns
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from
t
AOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
t
AONPD
ODT turn-on (Power-Down Modes)
t
AC.MIN + 2 ns
2
t
CK + tAC.MAX +1 ns
ns
t
AOFD
ODT turn-off delay
2.5
n
CK
t
AOF
ODT turn-off
t
AC.MIN
t
AC.MAX +0.6 ns
ns
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from
t
AOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5
ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
t
AOFPD
ODT turn-off (Power-Down Modes)
t
AC.MIN + 2 ns
2.5
t
CK + tAC.MAX +1ns
ns
t
ANPD
ODT to Power Down Mode Entry Latency
3
—
n
CK
t
AXPD
ODT Power Down Exit Latency
8
—
n
CK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HYS72T256322HP | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256322HP-3.7-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256322HP-3S-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256420HFD-3.7-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
| HYS72T256420HFD-3S-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
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