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参数资料
| 型号： | HYS72T256300EP-3.7-C |
| 厂商： | QIMONDA AG |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封装： | GREEN, RDIMM-240 |
| 文件页数： | 38/41页 |
| 文件大小： | 2780K |
| 代理商： | HYS72T256300EP-3.7-C |
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HYS72T256300EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
Internet Data Sheet
Rev. 1.0, 2007-07
6
07312007-34WH-CYDW
220
S2
I
SSTL
Rank 2 is selected by S2
NC
—
Not Connected
Note: 1-Rank, 2-Ranks module
221
S3
I
SSTL
Rank 3 is selected by S3
NC
—
Not Connected
Note: 1-Rank, 2-Ranks module
192
RAS
I
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
When sampled at the cross point of the rising edge of CK, and falling
edge of CK, RAS, CAS and WE define the operation to be executed by
the SDRAM.
74
CAS
I
SSTL
73
WE
I
SSTL
18
RESET
ICMOS
Register Reset
The RESET pin is connected to the RST pin on the register and to the
OE pin on the PLL. When LOW, all register outputs will be driven LOW
and the PLL clocks to the DRAMs and the register(s) will be set to low-
level. The PLL will remain synchronized with the input clock.
Address Signals
71
BA0
I
SSTL
Bank Address Bus 1:0
Selects internal SDRAM memory bank
190
BA1
I
SSTL
54
BA2
I
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
I
SSTL
Not Connected
Less than 1Gb DDR2 SDRAMS
188
A0
I
SSTL
Address Bus 12:0, Address Signal 10/AutoPrecharge
During a Bank Activate command cycle, defines the row address when
sampled at the crosspoint of the rising edge of CK and falling edge of
CK. During a Read or Write command cycle, defines the column
address when sampled at the cross point of the rising edge of CK and
falling edge of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is HIGH, autoprecharge is selected and BA[2:0] defines the
bank to be precharged. If AP is LOW, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with
BA[2:0] to control which bank(s) to precharge. If AP is HIGH, all banks
will be precharged regardless of the state of BA[2:0] inputs. If AP is
LOW, then BA[2:0] are used to define which bank to precharge.
183
A1
I
SSTL
63
A2
I
SSTL
182
A3
I
SSTL
61
A4
I
SSTL
60
A5
I
SSTL
180
A6
I
SSTL
58
A7
I
SSTL
179
A8
I
SSTL
177
A9
I
SSTL
70
A10
I
SSTL
AP
I
SSTL
57
A11
I
SSTL
176
A12
I
SSTL
196
A13
I
SSTL
Address Signal 13
NC
—
Not Connected
Note: Non CA parity modules based on 256 Mbit component
Pin No.
Name
Pin
Type
Buffer
Type
Function
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PDF描述 |
|---|---|
| HYS72T64300EP-3S-B2 | 64M X 72 DDR DRAM MODULE, DMA240 |
| HYS72T64400EFD-3S-B2 | 64M X 72 DDR DRAM MODULE, DMA240 |
| HZ24H2 | 24.15 V, 0.5 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-35 |
| HZ5HC2 | 5.1 V, 0.5 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-35 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HYS72T256322HP | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256322HP-3.7-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256322HP-3S-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256420HFD-3.7-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
| HYS72T256420HFD-3S-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
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