参数资料
型号: HYS72T256300EP-3.7-C
厂商: QIMONDA AG
元件分类: DRAM
英文描述: 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封装: GREEN, RDIMM-240
文件页数: 23/41页
文件大小: 2780K
代理商: HYS72T256300EP-3.7-C
HYS72T256300EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
Internet Data Sheet
Rev. 1.0, 2007-07
3
07312007-34WH-CYDW
1
Overview
This chapter gives an overview of the 240-pin Very Low Profile registered DDR2 SDRAM modules product family with parity
bit for address and control bus and describes its main characteristics.
1.1
Features
240-Pin PC2-6400, PC2-5300 and PC2-4200 DDR2
SDRAM memory modules.
One rank 256M
× 72 module organization and 256M × 4
chip organization
2GB Modules built with 1 Gbit DDR2 SDRAMs in chipsize
packages PG-TFBGA-60
Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
Programmable CAS Latencies (3, 4, 5 and 6 ), Burst
Length (8 & 4).
Auto Refresh (CBR) and Self Refresh
Auto Refresh for temperatures above 85 °C
t
REFI = 3.9 s.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
DCC enabling via EMRS2 setting.
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
Serial Presence Detect with E2PROM
Dimensions (nominal): 18.30 mm high, 133.35 mm wide
Based on standard reference layouts Raw Cards 'Z'
RoHS compliant products1)
TABLE 1
Performance Table
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
QAG Speed Code
–25F
–2.5
–3
–3S
–3.7
Unit
DRAM Speed Grade
DDR2
–800D
–800E
–667C
–667D
–533C
Module Speed Grade
PC2
–6400D
–6400E
–5300C
–5300D
–4200C
CAS-RCD-RP latencies
5–5–5
6–6–6
4–4–4
5–5–5
4–4–4
t
CK
Max.
Clock Frequency
CL3
f
CK3
200
MHz
CL4
f
CK4
266
333
266
MHz
CL5
f
CK5
400
333
266
MHz
CL6
f
CK6
–400
––MHz
Min. RAS-CAS-Delay
t
RCD
12.5
15121515ns
Min. Row Precharge Time
t
RP
12.5
15121515ns
Min. Row Active Time
t
RAS
45
ns
Min. Row Cycle Time
t
RC
57.5
60576060ns
相关PDF资料
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HYS72T64300EP-3S-B2 64M X 72 DDR DRAM MODULE, DMA240
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