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| 型号： | HYS72T256300EP-3.7-C |
| 厂商： | QIMONDA AG |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封装： | GREEN, RDIMM-240 |
| 文件页数： | 9/41页 |
| 文件大小： | 2780K |
| 代理商： | HYS72T256300EP-3.7-C |
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HYS72T256300EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
Internet Data Sheet
Rev. 1.0, 2007-07
17
07312007-34WH-CYDW
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until
V
REF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ
4) The output timing reference voltage level is
V
TT.
5)
t
RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
3.3.2
Component AC Timing Parameters
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–800
Parameter
Symbol
DDR2–800
Unit
Notes1)2)3)4)5)6)
7)8)
Min.
Max.
DQ output access time from CK / CK
t
AC
–400
+400
ps
9)
CAS to CAS command delay
t
CCD
2—
nCK
Average clock high pulse width
t
CH.AVG
0.48
0.52
t
CK.AVG
10)11)
Average clock period
t
CK.AVG
2500
8000
ps
CKE minimum pulse width ( high and low pulse
width)
t
CKE
3—
nCK
12)
Average clock low pulse width
t
CL.AVG
0.48
0.52
t
CK.AVG
Auto-Precharge write recovery + precharge time
t
DAL
WR +
t
nRP
—nCK
13)14)
Minimum time clocks remain ON after CKE
asynchronously drops LOW
t
DELAY
t
IS + tCK .AVG +
t
IH
––
ns
DQ and DM input hold time
t
DH.BASE
125
––
ps
19)20)15)
DQ and DM input pulse width for each input
t
DIPW
0.35
—
t
CK.AVG
DQS output access time from CK / CK
t
DQSCK
–350
+350
ps
DQS input high pulse width
t
DQSH
0.35
—
t
CK.AVG
DQS input low pulse width
t
DQSL
0.35
—
t
CK.AVG
DQS-DQ skew for DQS & associated DQ signals
t
DQSQ
—200
ps
16)
DQS latching rising transition to associated clock
edges
t
DQSS
– 0.25
+ 0.25
t
CK.AVG
17)
DQ and DM input setup time
t
DS.BASE
50
––
ps
18)19)20)
DQS falling edge hold time from CK
t
DSH
0.2
—
t
CK.AVG
DQS falling edge to CK setup time
t
DSS
0.2
—
t
CK.AVG
Four Activate Window for 1KB page size products
t
FAW
35
—
ns
Four Activate Window for 2KB page size products
t
FAW
45
—
ns
CK half pulse width
t
HP
Min(
t
CH.ABS,
t
CL.ABS)
__
ps
21)
Data-out high-impedance time from CK / CK
t
HZ
—
t
AC.MAX
ps
9)22)
Address and control input hold time
t
IH.BASE
250
—
ps
23)25)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HYS72T256322HP | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256322HP-3.7-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256322HP-3S-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256420HFD-3.7-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
| HYS72T256420HFD-3S-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
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