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参数资料
| 型号： | HYS72T256300EP-3.7-C |
| 厂商： | QIMONDA AG |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封装： | GREEN, RDIMM-240 |
| 文件页数： | 22/41页 |
| 文件大小： | 2780K |
| 代理商： | HYS72T256300EP-3.7-C |
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HYS72T256300EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
Internet Data Sheet
Rev. 1.0, 2007-07
29
07312007-34WH-CYDW
3.4
I
DD Specifications and Conditions
List of tables defining
I
DD Specifications and Conditions.
TABLE 19
I
DD Measurement Conditions
Parameter
Symbol Note1)2)
3)4)5)
Operating Current 0
One bank Active - Precharge;
t
CK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
I
DD0
Operating Current 1
One bank Active - Read - Precharge;
I
OUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
I
DD1
6)
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
I
DD2N
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
I
DD2P
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
I
DD2Q
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
OUT = 0 mA.
I
DD3N
Active Power-Down Current
All banks open;
t
CK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
I
DD3P(0)
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
I
DD3P(1)
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX;
t
RP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING;
I
OUT = 0mA.
I
DD4R
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
DD4W
Burst Refresh Current
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I
DD5B
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HYS72T256322HP | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256322HP-3.7-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256322HP-3S-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256420HFD-3.7-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
| HYS72T256420HFD-3S-A | 制造商:QIMONDA 制造商全称:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
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