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参数资料
| 型号： | IBIS4-A-6600 |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | 6.6 MP CMOS Image Sensor |
| 中文描述： | 6.6万像素的CMOS图像传感器 |
| 文件页数： | 21/40页 |
| 文件大小： | 1698K |
| 代理商： | IBIS4-A-6600 |
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IBIS4-A-6600
CYII4SM6600AB
ADVANCE
INFORMATION
Document Number: 001-02366 Rev. *D
Page 21 of 40
Detailed Description of Registers
SEQUENCEHR Register
a. NDR (bit 0)
In normal operation (NDR = 0), the sensor operates in double
sampling mode. At the start of each row readout, the signals
from the pixels are sampled, the row is reset and the signals
from the pixels are sampled again. The values are subtracted
in the output amplifier.
When NDR is set to 1, the sensor operates in non-destructive
readout (NDR) mode (see Table 16. ).
b. NDR_mode (bit 1 and 2)
7 (0111)
7:0
1:0
IMAGE CORE register
TEST_mode
Default value <7:0>:"00000000"
LSB: odd, MSB: even
0 = normal operation
sub-sampling mode in X-direction
sub-sampling mode in X-direction
Default value <9:0>:"0000010000"
Output amplifier gain setting
0 = gain setting by GAIN<3:0>
1 = unity gain setting
0 = two analog outputs
1 = multiplexing to one output (out_1)
0 = normal operation
1 = amplifier in standby mode.
Delay of pixel clock to output amplifier.
Amplifier DAC raw offset.
Default value <7:0>:"10000000"
Amplifier DAC fine offset.
Default value <7:0>:"10000000"
DAC dark reference on output bus.
Default value <7:0>:"10000000"
Default value <10:0>:"00000000000"
0 = normal operation
1 = ADC in standby
4:2
7:5
9:0
3:0
4
X_SUBSAMPLE
Y_SUBSAMPLE
AMPLIFIER register
GAIN<3:0>
UNITY
8 (1000)
5
ONE_OUT
6
STANDBY
7:9
7:0
DELAY_CLK_AMP
DAC_RAW_REG
9 (1001)
10 (1010)
7:0
DAC_FINE_REG
11 (1011)
7:0
DAC_DARK_REG
12 (1100)
10:0
0
ADC register
STANDBY_1
1
2
STANDBY_2
ONE
0 = multiplexing of two ADC outputs
1 = disable multiplexing
if ONE = 0: delay of output with one (EXT_CLK = 0) or half (EXT_CLK = 1)
clock cycle
if ONE = 1: switch between two ADCs
0 = internal clock (same as clock to X shift register and output amplifier)
1 = external clock
0 = normal operation
1 = outputs in tristate mode
Delay of clock to ADCs and digital multiplexer
0 = linear conversion
1 = 'gamma' law conversion
0 = no inversion of bits
1 = inversion of bits
3
SWITCH
4
EXT_CLK
5
TRISTATE
6:8
9
DELAY_CLK_ADC
GAMMA
10
BITINVERT
13 (1101)
14 (1110)
15 (1111)
Reserved.
Reserved.
Reserved.
Table 15. List of Internal Registers
(continued)
Register
Bit
Name
Description
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相关代理商/技术参数 |
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|---|---|
| IBIS4-A-6600-C-2 | 制造商:Cypress Semiconductor 功能描述:IMAGE SENSOR COLOR CMOS 2210X3002PIXELS - Bulk |
| IBIS4-A-6600-M-2 | 制造商:Cypress Semiconductor 功能描述:IMAGE SENSOR MONOCHROME CMOS 2210X3002PIXELS - Bulk |
| IBIS5-A-1300-C-1 | 制造商:Cypress Semiconductor 功能描述:IMAGE SENSOR COLOR CMOS 1280X1024PIXELS 84PIN LCC - Bulk |
| IBIS5-A-1300-C-2 | 制造商:Cypress Semiconductor 功能描述:Image Sensor Color CMOS 1280x1024Pixels 84-Pin LCC 制造商:Cypress Semiconductor 功能描述:IMAGE SENSOR COLOR CMOS 1280X1024PIXELS 84PIN LCC - Bulk |
| IBIS5-A-1300-M-1 | 制造商:Cypress Semiconductor 功能描述:Image Sensor Monochrome CMOS 1280x1024Pixels 84-Pin LCC 制造商:Cypress Semiconductor 功能描述:IMAGE SENSOR MONOCHROME CMOS 1280X1024PIXELS 84PIN LCC - Bulk |
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