参数资料
型号: IBM0116165B
厂商: IBM Microeletronics
英文描述: 1M x 16 12/8 EDO DRAM(16M位 动态RAM(超页面模式读写并带20条地址线,其中12条为行地址选通,8条为列地址选通))
中文描述: 100万× 16 12 / 8 EDO公司的DRAM(1,600位动态随机存储器(超页面模式读写并带20条地址线,其中12条为行地址选通,8条为列地址选通))
文件页数: 7/31页
文件大小: 553K
代理商: IBM0116165B
IBM0116165
IBM0116165B IBM0116165P
1M x 16 12/8 EDO DRAM
IBM0116165M
28H4723
SA14-4225-06
Revised 4/97
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 31
AC Characteristics
(T
A
= 0 to +70C, V
CC
= 3.3V
±
0.3V or V
CC
= 5.0V
±
0.5V)
1. An initial pause of 200
μ
s is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using the internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only
refresh cycles is required.
2. AC measurements assume t
T
=2ns.
3. V
IH
(min.) and V
IL
(max.) are reference levels for measuring timing of input signals. Also, transition times are measured between V
IH
and V
IL
.
4. Valid column addresses A0 through A7.
5. When both LCAS and UCAS go low at the same time, all 16 bits of data are read/written into the device. LCAS and UCAS cannot be
staggered within the same Read/Write cycle.
Read, Write, Read-Modify-Write and Refresh Cycles
(Common Parameters)
Symbol
Parameter
-50
-60
Units
Notes
Min.
Max.
Min.
Max.
t
RC
Random Read or Write Cycle Time
84
104
ns
t
RP
RAS Precharge Time
30
40
ns
t
CP
CAS Precharge Time
8
10
ns
t
RAS
RAS Pulse Width
50
10K
60
10K
ns
t
CAS
CAS Pulse Width
8
10K
10
10K
ns
t
ASR
Row Address Setup Time
0
0
ns
t
RAH
Row Address Hold Time
10
10
ns
t
ASC
Column Address Setup Time
0
0
ns
t
CAH
Column Address Hold Time
8
_
10
ns
t
RCD
RAS to CAS Delay Time
14
37
14
45
ns
1
t
RAD
RAS to Column Address Delay Time
12
25
12
30
ns
2
t
RSH
RAS Hold Time
8
10
ns
t
CSH
CAS Hold Time
38
45
ns
t
CRP
CAS to RAS Precharge Time
5
5
ns
t
DZO
OE Delay Time from D
IN
0
0
ns
3
t
DZC
CAS Delay Time from D
IN
0
0
ns
3
t
T
Transition Time (Rise and Fall)
2
50
2
50
ns
4
1. Operation within the t
RCD
(max.) limit ensures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(max.) limit, then access time is controlled by t
CAC
.
2. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as a reference point only. If t
RAD
is
greater than the specified t
RAD
(max.) limit, then access time is controlled by t
AA
.
3. Either t
DZC
or t
DZO
must be satisfied.
4. AC measurements assume t
T
=2ns.
Discontinued (9/98 - last order; 3/99 last ship)
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