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参数资料
型号： ICS93727YFLF-T
元件分类： 时钟及定时
英文描述： PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 10 INVERTED OUTPUT(S), PDSO48
封装： 0.300 INCH, SSOP-48
文件页数： 2/9页
文件大小： 109K
代理商： ICS93727YFLF-T
2
ICS93727
Preliminary Product Preview
0711B—10/10/02
Pin Descriptions
PIN
#
NAME
TYPE
1
GND
PWR
Ground pin.
2
DDRC0
OUT
"Complementary" Clock of differential pair output.
3
DDRT0
OUT
"True" Clock of differential pair output.
4
VDD2.5
PWR
Power supply, nominal 2.5V
5
DDRT1
OUT
"True" Clock of differential pair output.
6
DDRC1
OUT
"Complementary" Clock of differential pair output.
7
GND
PWR
Ground pin.
8
GND
PWR
Ground pin.
9
DDRC2
OUT
"Complementary" Clock of differential pair output.
10
DDRT2
OUT
"True" Clock of differential pair output.
11
VDD2.5
PWR
Power supply, nominal 2.5V
12
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
13
CLK_IN
IN
Reference clock input.
14
**FS_PROG0
IN
Latch input pin to change Byte 1 bit 7 Fine Skew Programming default polarity (Pulling this bit
low will set DDR output to be advance vs the input).
15
VDD2.5
PWR
Power supply, nominal 2.5V
16
AVDD
PWR
2.5V Analog Power pin for Core PLL
17
AGND
PWR
Analog Ground pin for Core PLL
18
GND
PWR
Ground pin.
19
DDRC3
OUT
"Complementary" Clock of differential pair output.
20
DDRT3
OUT
"True" Clock of differential pair output.
21
VDD2.5
PWR
Power supply, nominal 2.5V
22
DDRT4
OUT
"True" Clock of differential pair output.
23
DDRC4
OUT
"Complementary" Clock of differential pair output.
24
GND
PWR
Ground pin.
25
GND
PWR
Ground pin.
26
DDRC9
OUT
"Complementary" Clock of differential pair output.
27
DDRT9
OUT
"True" Clock of differential pair output.
28
VDD2.5
PWR
Power supply, nominal 2.5V
29
DDRT8
OUT
"True" Clock of differential pair output.
30
DDRC8
OUT
"Complementary" Clock of differential pair output.
31
GND
PWR
Ground pin.
32
CS_PROG0**
IN
Latch input pin to change Byte 3 bit 5 Coarse Skew Programming default (Pulling this bit high will
advance the DDR output vs the input, refer to table 1 for timing details).
33
RSTEP
IN
Exnterna pull-down resistor can be set on this pin to program input vs DDR clocks skew.
34
VDD2.5
PWR
Power supply, nominal 2.5V
35
RFIX
IN
Exnterna pull-down resistor can be set on this pin to program input vs DDR clocks skew.
36
CS_PROG1*
IN
Latch input pin to change Byte 3 bit 7 Coarse Skew Programming default (Pulling this bit high will
advance the DDR output vs the input, refer to table 1 for timing details).
37
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
38
VDD2.5
PWR
Power supply, nominal 2.5V
39
DDRT7
OUT
"True" Clock of differential pair output.
40
DDRC7
OUT
"Complementary" Clock of differential pair output.
41
GND
PWR
Ground pin.
42
GND
PWR
Ground pin.
43
DDRC6
OUT
"Complementary" Clock of differential pair output.
44
DDRT6
OUT
"True" Clock of differential pair output.
45
VDD2.5
PWR
Power supply, nominal 2.5V
46
DDRT5
OUT
"True" Clock of differential pair output.
47
DDRC5
OUT
"Complementary" Clock of differential pair output.
48
GND
PWR
Ground pin.
DESCRIPTION
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