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参数资料
| 型号： | IDT5T2010BBGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| 封装： | GREEN, PLASTIC, BGA-144 |
| 文件页数： | 1/24页 |
| 文件大小： | 201K |
| 代理商： | IDT5T2010BBGI |
1
INDUSTRIALTEMPERATURERANGE
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
1sOE
2sOE
1
Q0
1
Q1
2
Q0
2
Q1
3
Q0
3
Q1
4
Q0
4
Q1
5
Q0
5
Q1
QFB
Divide
Select
1F2:1
Divide
Select
2F2:1
Divide
Select
3F2:1
Divide
Select
4F2:1
Divide
Select
5F2:1
TxS
REF0
REF0/
VREF0
FB
FB/
VREF2
RxS
REF1
REF1/
VREF1
0
1
PLL
PD
FS
LOCK
PE
PLL_EN
/N
DS1:0
3
REF_SEL
0
1
Divide
Select
FBF2:1
OMODE
3sOE
4sOE
5sOE
MARCH 2006
2006
Integrated Device Technology, Inc.
DSC 5981/29
c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
2.5 VDD
5 pairs of outputs
Low skew: 50ps same pair, 100ps all outputs
Selectable positive or negative edge synchronization
Tolerant of spread spectrum input clock
Synchronous output enable
Selectable inputs
Input frequency: 4.17MHz to 250MHz
Output frequency: 12.5MHz to 250MHz
1.8V / 2.5V LVTTL: up to 250MHz
HSTL / eHSTL: up to 250MHz
Hot insertable and over-voltage tolerant inputs
3-level inputs for selectable interface
3-level inputs for feedback divide selection with multiply ratios
of(1-6, 8, 10, 12)
Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
Selectable differential or single-ended inputs and ten single-
ended outputs
PLL bypass for DC testing
External differential feedback, internal loop filter
Low Jitter: <75ps cycle-to-cycle
Power-down mode
Lock indicator
Available in BGA and VFQFPN packages
FUNCTIONAL BLOCK DIAGRAM
IDT5T2010
2.5V ZERO DELAY PLL
CLOCK DRIVER TERACLOCK
DESCRIPTION:
The IDT5T2010 is a 2.5V PLL clock driver intended for high perfor-
mance computing and data-communications applications. The IDT5T2010
has ten outputs in five banks of two, plus a dedicated differential feedback.
The redundant input capability allows for a smooth change over to a
secondary clock source when the primary clock source is absent.
The feedback bank allows divide-by-functionality from 1 to 12 through
the use of the DS[1:0] inputs. This provides the user with frequency
multiplication 1 to 12 without using divided outputs for feedback. Each output
bank also allows for a divide-by functionality of 2 or 4.
The IDT5T2010 features a user-selectable, single-ended or differential
inputtotensingle-endedoutputs. Theclockdriveralsoactsasatranslatorfrom
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended
1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs.
Selectableinterfaceiscontrolledby3-levelinputsignalsthatmaybehard-wired
to appropriate high-mid-low levels. The outputs can be synchronously
enabled/disabled.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT5T2010BBI8 | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| IDT5T9010BBGI | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| IDT5T9010BBI | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| IDT5T9010BBI8 | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| IDT5T905PGGI | 5T SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT5T2010BBGI8 | 功能描述:IC CLK DVR ZD PLL 2.5V 144-BGA RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:TeraClock™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| IDT5T2010BBI | 功能描述:IC CLK DVR ZD PLL 2.5V 144-BGA RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:TeraClock™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| IDT5T2010NLGI | 功能描述:IC CLK DVR ZD PLL 2.5V 68-VFQFPN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:TeraClock™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| IDT5T2010NLGI8 | 功能描述:IC CLK DVR ZD PLL 2.5V 68-VFQFPN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:TeraClock™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| IDT5T2110BBGI | 功能描述:IC CLK DVR 2.5V PLL DIFF 144BGA RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:TeraClock™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
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