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| 型号： | IDT5T2010BBGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| 封装： | GREEN, PLASTIC, BGA-144 |
| 文件页数： | 7/24页 |
| 文件大小： | 201K |
| 代理商： | IDT5T2010BBGI |
15
INDUSTRIALTEMPERATURERANGE
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol
Parameter
Value
Units
VIH
Input HIGH Voltage(1)
VDDI
V
VIL
Input LOW Voltage
0V
VTHI
Input Timing Measurement Reference Level(2)
VDDI/2
mV
tR, tF
Input Signal Edge Rate(3)
2
V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol
Parameter
Value
Units
VDIF
Input Signal Swing(1)
VDDI
V
VX
Differential Input Signal Crossing Point(2)
VDDI/2
mV
VTHI
Input Timing Measurement Reference Level(3)
Crossing Point
V
tR, tF
Input Signal Edge Rate(4)
1.8
V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable
results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions.
2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
POWER SUPPLY CHARACTERISTICS FOR 1.8V LVTTL OUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQ = Max., REF = LOW,
PD = HIGH, nSOE = LOW,
15
25
mA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
IDDQQ
Quiescent VDDQ Power Supply Current(3)
VDDQ = Max., REF = LOW,
PD = HIGH, nSOE = LOW,
1.5
50
μA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
IDDPD
Power Down Current
VDD = Max.,
PD = LOW, nSOE = LOW, PLL_EN = HIGH
0.5
3
mA
IDDD
Dynamic VDD Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
16
25
μA/MHz
CurrentperOutput
IDDDQ
Dynamic VDDQ Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
22
30
μA/MHz
CurrentperOutput
ITOT
Total Power VDD Supply Current(4)
VDDQ = 1.8V., FVCO = 100MHz, CL = 15pF
40
60
mA
VDDQ = 1.8V., FVCO = 250MHz, CL = 15pF
70
105
ITOTQ
Total Power VDDQ Supply Current(4)
VDDQ = 1.8V., FVCO = 100MHz, CL = 15pF
55
85
mA
VDDQ = 1.8V., FVCO = 250MHz, CL = 15pF
135
205
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH.
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