参数资料
型号: IDT70T633S10BCI
厂商: IDT, Integrated Device Technology Inc
文件页数: 16/27页
文件大小: 0K
描述: IC SRAM 9MBIT 10NS 256BGA
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 9M(512K x 18)
速度: 10ns
接口: 并联
电源电压: 2.4 V ~ 2.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 256-LBGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
其它名称: 70T633S10BCI
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Symbol
Parameter
70T633/1S10
Com'l
& Ind (6)
Min. Max.
70T633/1S12
Com'l
& Ind
Min. Max.
70T633/1S15
Com'l Only
Min. Max.
Unit
BUSY TIMING (M/ S =V IH )
t BAA
t BDA
t BAC
t BDC
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
____
____
____
____
10
10
10
10
____
____
____
____
12
12
12
12
____
____
____
____
15
15
15
15
ns
ns
ns
ns
t APS
Arbitration Priority Set-up Time
(2)
2.5
____
2.5
____
2.5
____
ns
Write Hold After BUSY
t BDD
t WH
BUSY Disable to Valid Data
(5)
(3)
____
7
10
____
____
9
12
____
____
12
15
____
ns
ns
BUSY TIMING (M/ S =V IL )
Write Hold After BUSY
t WB
t WH
BUSY Input to Write (4)
(5)
0
7
____
____
0
9
____
____
0
12
____
____
ns
ns
PORT-TO-PORT DELAY TIMING
t WDD
Write Pulse to Data Delay (1)
____
14
____
16
____
20
ns
t DDD
Write Data Valid to Read Data Delay
(1)
____
14
____
16
____
20
ns
NOTES:
5670 tbl 15
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/ S = V IH )".
2. To ensure that the earlier of the two ports wins.
3. t BDD is a calculated parameter and is the greater of the Max. spec, t WDD – t WP (actual), or t DDD – t DW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (1,2,3)
Symbol
Parameter
70T633/1S10
Com'l
& Ind
Min. Max.
70T6331S12
Com'l
& Ind
Min. Max.
70T633/1S15
Com'l Only
Min. Max.
SLEEP MODE TIMING (ZZx=V IH )
t ZZS
t ZZR
t ZZPD
t ZZPU
Sleep Mode Set Time
Sleep Mode Reset Time
Sleep Mode Power Down Time (4)
Sleep Mode Power Up Time (4)
10
10
10
____
____
____
____
0
12
12
12
____
____
____
____
0
15
15
15
____
____
____
____
0
5670 tbl 15a
NOTES:
1. Timing is the same for both ports.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INT x, M/ S and the sleep mode pins themselves (ZZx) are not affected
during sleep mode. It is recommended that boundary scan not be operated during sleep mode.
3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details.
4. This parameter is guaranteed by device characterization, but is not production tested.
16
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