参数资料
型号: IDT70T633S10BCI
厂商: IDT, Integrated Device Technology Inc
文件页数: 18/27页
文件大小: 0K
描述: IC SRAM 9MBIT 10NS 256BGA
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 9M(512K x 18)
速度: 10ns
接口: 并联
电源电压: 2.4 V ~ 2.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 256-LBGA
供应商设备封装: 256-CABGA(17x17)
包装: 托盘
其它名称: 70T633S10BCI
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (M/ S = V IH ) (1)
ADDR "A"
and "B"
CE "A"(3)
CE "B"(3)
t APS (2)
ADDRESSES MATCH
t BAC
t BDC
BUSY "B"
.
5670 drw 16
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/ S = V IH ) (1,3,4)
ADDR "A"
ADDR "B"
ADDRESS "N"
t APS (2)
MATCHING ADDRESS "N"
t BAA
t BDA
BUSY "B"
5670 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If t APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. CE X = V IL when CE 0X = V IL and CE 1X = V IH . CE X = V IH when CE 0X = V IH and/or CE 1X = V IL .
4. CE 0X = OE X = LB X = UB X = V IL . CE 1X = V IH .
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (1,2)
70T633/1S10
Com'l
& Ind
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
t AS
t WR
t INS
t INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
Interrupt Reset Time
0
0
____
____
____
____
10
10
0
0
____
____
____
____
12
12
0
0
____
____
____
____
15
15
ns
ns
ns
ns
5670 tbl 16
NOTES:
1. Timing is the same for both ports.
2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details.
18
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