- 您现在的位置：买卖IC网 > PDF目录3955 > IDT70V3599S166DR (IDT, Integrated Device Technology Inc)IC SRAM 4MBIT 166MHZ 208QFP PDF资料下载
参数资料
| 型号： | IDT70V3599S166DR |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 14/23页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 4MBIT 166MHZ 208QFP |
| 标准包装： | 6 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，同步 |
| 存储容量： | 4.5M（128K x 36） |
| 速度： | 166MHz |
| 接口： | 并联 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
| 包装： | 托盘 |
| 其它名称： | 70V3599S166DR |
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read (1,2,4)
CLK "A"
R/ W "A"
t SW
t SA
t HW
t HA
ADDRESS "A"
DATA IN"A"
MATCH
t SD
t HD
VALID
NO
MATCH
t CO (3)
CLK "B"
t CD2
R/ W "B"
t SW
t SA
t HW
t HA
ADDRESS "B"
DATA OUT"B"
MATCH
NO
MATCH
VALID
NOTES:
t DC
5617 drw 10
1. CE 0 , BE n , and ADS = V IL ; CE 1 and REPEAT = V IH .
2. OE = V IL for Port "B", which is being read from. OE = V IH for Port "A", which is being written to.
3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
t CO + 2 t CYC2 + t CD2 ). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be t CO + t CYC2 + t CD2 ).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read (1,2,4)
CLK "A"
R/ W "A"
t SW
t SA
t HW
t HA
ADDRESS "A"
DATA IN "A"
MATCH
t SD
t HD
VALID
t CO
(3)
NO
MATCH
CLK "B"
t CD1
R/ W "B"
t SW
t SA
t HW
t HA
ADDRESS "B"
MATCH
NO
MATCH
t CD1
DATA OUT "B"
NOTES:
t DC
VALID
t DC
VALID
5617 drw 11
1. CE 0 , BE n, and ADS = V IL ; CE 1 and REPEAT = V IH .
2. OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to.
3. If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
t CO + t CYC + t CD1 ). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be t CO + t CD1 ).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
14
6.42
相关PDF资料 |
PDF描述 |
|---|---|
| IDT70V3319S166PRF | IC SRAM 4MBIT 166MHZ 128TQFP |
| 356-006-525-101 | CARDEDGE 6POS .156 BLACK |
| 356-006-521-104 | CARDEDGE 6POS .156 BLACK |
| 356-006-521-102 | CARDEDGE 6POS .156 BLACK |
| 1-84953-8 | CONN FPC 18POS 1MM RT ANG SMD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT70V3599S166DRG | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 4.5MBIT 166MHZ 208PQFP |
| IDT70V35L15PF | 功能描述:IC SRAM 144KBIT 15NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT70V35L15PF8 | 功能描述:IC SRAM 144KBIT 15NS 100TQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:45 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，异步 存储容量:128K（8K x 16） 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x14） 包装:托盘 其它名称:70V25S15PF |
| IDT70V35L15PFG | 功能描述:IC SRAM 144KBIT 15NS 100TQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 双端口，同步 存储容量:1.125M（32K x 36） 速度:5ns 接口:并联 电源电压:3.15 V ~ 3.45 V 工作温度:-40°C ~ 85°C 封装/外壳:256-LBGA 供应商设备封装:256-CABGA（17x17） 包装:带卷 (TR) 其它名称:70V3579S5BCI8 |
| IDT70V35L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 144KBIT 15NS 100TQFP |
发布紧急采购，3分钟左右您将得到回复。