参数资料
型号: IDT70V3599S166DR
厂商: IDT, Integrated Device Technology Inc
文件页数: 18/23页
文件大小: 0K
描述: IC SRAM 4MBIT 166MHZ 208QFP
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 4.5M(128K x 36)
速度: 166MHz
接口: 并联
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
包装: 托盘
其它名称: 70V3599S166DR
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs) (1)
t CYC2
CLK
t CH2
t CL2
t SA
t HA
ADDRESS
An
INTERNAL (3)
ADDRESS
An (7)
An + 1
An + 2
An + 3
An + 4
t SAD t HAD
ADS
t SCN t HCN
CNTEN
t SD t HD
DATA IN
Dn
Dn + 1
Dn + 1
Dn + 2
Dn + 3
Dn + 4
WRITE
EXTERNAL
ADDRESS
WRITE WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
5617 drw 18
Timing Waveform of Counter Repeat (2)
t CYC2
t CH2
t CL2
CLK
t SA t HA
(4)
ADDRESS
An
An + 1
An + 2
INTERNAL (3)
ADDRESS
Ax
LAST ADS LOAD
LAST ADS +1
An
An + 1
t SW t HW
R/ W
ADS
CNTEN
t SRPT t HRPT
t SAD t HAD
t SCN t HCN
REPEAT
DATA IN
(5)
t SD
t HD
D 0
DATA OUT
Q LAST
Q LAST+1
Qn
EXECUTE
REPEAT
(6)
WRITE
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS + 1
READ
ADDRESS n
READ
ADDRESS n+1
5617 drw 19
NOTES:
1. CE 0 , BE n , and R/ W = V IL ; CE 1 and REPEAT = V IH .
2. CE 0 , BE n = V IL ; CE 1 = V IH .
3. The "Internal Address" is equal to the "External Address" when ADS = V IL and equals the counter output when ADS = V IH .
4. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
7. CNTEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
18
6.42
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