参数资料
型号: IDT70V3599S166DR
厂商: IDT, Integrated Device Technology Inc
文件页数: 5/23页
文件大小: 0K
描述: IC SRAM 4MBIT 166MHZ 208QFP
标准包装: 6
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,同步
存储容量: 4.5M(128K x 36)
速度: 166MHz
接口: 并联
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
包装: 托盘
其它名称: 70V3599S166DR
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Pin Names
Industrial and Commercial Temperature Ranges
Left Port
Right Port
Names
CE 0L , CE 1L
CE 0R , CE 1R
Chip Enables
(5)
R/ W L
OE L
R/ W R
OE R
Read/Write Enable
Output Enable
A 0L - A 16L
(1)
A 0R - A 16R
(1)
Address
I/O 0L - I/O 35L
CLK L
PL/ FT L
ADS L
CNTEN L
REPEAT L
BE 0L - BE 3L
I/O 0R - I/O 35R
CLK R
PL/ FT R
ADS R
CNTEN R
REPEAT R
BE 0R - BE 3R
Data Input/Output
Clock
Pipeline/Flow-Through
Address Strobe Enable
Counter Enable
Counter Repeat (4)
Byte Enables (9-bit bytes) (5)
V DDQL
OPT L
V DD
V SS
TDI
V DDQR
OPT R
Power (I/O Bus) (3.3V or 2.5V) (2)
Option for selecting V DDQX (2,3)
Power (3.3V) (2)
Ground (0V)
Test Data Input
NOTES:
1. A 16 is a NC for IDT70V3589.
2. V DD , OPT X , and V DDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
3. OPT X selects the operating voltage levels for the I/Os and controls on that port.
If OPT X is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V DDQX must be supplied at 3.3V. If OPT X is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and V DDQX must be
TDO
TCK
TMS
TRST
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
5617 tbl 01
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
4. When REPEAT X is asserted, the counter will reset to the last valid address loaded
via ADS X .
5. Chip Enables and Byte Enables are double buffered when PL/ FT = V IH , i.e., the
signals take two cycles to deselect.
5
6.42
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