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| 型号： | IDT70V5388S133BC8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 22/29页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 1.125MBIT 133MHZ 256BGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 四端口，同步 |
| 存储容量： | 1.125M（64K x 18） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-CABGA（17x17） |
| 包装： | 带卷 (TR) |
| 其它名称： | 70V5388S133BC8 |
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IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort? Static RAM
Mailbox Interrupts
The IDT70V5388/78 supports mailbox interrupts,
facilitating communication among the devices attached to
each port. If the user chooses the interrupt function, then
each of the upper four address locations in the memory
array are assigned as a mailbox for one of the ports: FFFFh
(7FFFh for IDT70V5378) is the mailbox for Port 1, FFFEh
(7FFEh for IDT70V5378) is the mailbox for Port 2, FFFDh
(7FFDh for IDT70V5378) is the mailbox for Port 3, and
FFFCh (7FFCh for IDT70V5378) is the mailbox for Port 4.
Truth Table III details the operation of the mailbox interrupt
functions.
A given port’s interrupt is set (i.e., INT goes LOW)
whenever any other port on the device writes to the given
port’s address. For example, Port 1’s INT will go LOW if Port
2, Port 3, or Port 4 write to FFFFh (7FFFh for IDT70V5378).
The INT will go LOW in relation to the clock on the writing
port (see also the Mailbox Interrupt Timing waveform on
page 20). If a port writes to its own mailbox, no interrupt is
generated.
The mailbox location is a valid memory address:
the user can store an 18-bit data word at that location for
retrieval by the target port. In the event that two or more ports
attempt to set an interrupt to the same port at the same
time, the interrupt signal will go LOW, but the data actually
stored at that location will be indeterminate. The actual
interrupt is generated as a result of evaluating the state of
the address pins, the chip enables, and the R/ W pin: if the
user wishes to set an interrupt to a specific port without
changing the data stored in that port’s mailbox, it is
Industrial and Commercial Temperature Ranges
possible to do so by disabling the byte enables during that
write cycle.
Once INT has gone LOW for a specific port, that
port can reset the INT by reading its assigned mailbox. In
the case of Port 1, it would clear its INT signal by reading
FFFFh (7FFFh for IDT70V5378). As stated previously, the
interrupt operation executes based on the state of the
address pins, the chip enables, and the R/ W pin: it is
possible to clear the interrupt by asserting a read to the
appropriate location while keeping the output enable ( OE ) or
the byte enables deasserted, and so avoid having to drive
data on the I/O bus. The INT is reset, or goes HIGH again,
in relation to the reading port’s clock signal.
Master Reset
The IDT70V5388/78 is equipped with an asynchro-
nous Master Reset input, which can be asserted indepen-
dently of all clock inputs and will take effect per the Master
Reset timing waveform on page 18. The Master Reset sets
the internal value of all address counters to zero, and sets
the counter mask register on each port to all ones (i.e.,
completely unmasked). It also resets all mailbox interrupts
and counter interrupts to HIGH (i.e., non-asserted) and
sets all registered control signals to a deselected state. A
Master Reset operation must be performed after power-up,
in order to initialize the various registers on the device to a
known state. Master Reset will reset the device. For JTAG
and MBIST reset please refer to the JTAG Section on page
25.
Truth Table III — Mailbox Interrupt Flag Operations
Port 1 (1,2)
Port 2 (1,2)
Port 3 (1,2)
Port 4 (1,2)
R/ W
X
H
L
X
L
X
L
X
CE
X
L
L
X
L
X
L
X
A 15- A 0(4)
X
FFFF
FFFE
X
FFFD
X
FFFC
X
INT
L
H
X
X
X
X
X
X
R/ W
L
X
X
H
L
X
L
X
CE
L
X
X
L
L
X
L
X
A 15- A 0(4)
FFFF
X
X
FFFE
FFFD
X
FFFC
X
INT
X
X
L
H
X
X
X
X
R/ W
L
X
L
X
X
H
L
X
CE
L
X
L
X
X
L
L
X
A 15- A 0(4)
FFFF
X
FFFE
X
X
FFFD
FFFC
X
INT
X
X
X
X
L
H
X
X
R/ W
L
X
L
X
L
X
X
H
CE
L
X
L
X
L
X
X
L
A 15- A 0(4)
FFFF
X
FFFE
X
FFFD
X
X
FFFC
INT
X
X
X
X
X
X
L
H
Function
Set Port 1 INT Flag (3)
Reset Port 1 INT Flag
Set Port 2 INT Flag (3)
Reset Port 2 INT Flag
Set Port 3 INT Flag (3)
Reset Port 3 INT Flag
Set Port 4 INT Flag (3)
Reset Port 4 INT Flag
NOTES:
5649 tbl 14
1. The status of OE is a "Don't Care" for the interrupt logic circuitry. If it is desirable to reset the interrupt flag on a given port while keeping the I/O bus in a tri-state
condition, then this can be accomplished by setting OE = V IH while the read access is asserted to the appropriate address location.
2. The status of the LB and UB controls are "Don't Care" for the interrupt circuitry. If it is desirable to set the interrupt flag to a specific port without overwriting the
data value already stored at the mailbox location, then this can be accomplished by setting LB = UB = V IH during the write access for that specific mailbox.
Similarly, if it desirable to reset the interrupt flag on a given port while keeping the I/O bus in a tri-state condition, then this can be accomplished by setting LB
= UB = V IH while the read access is asserted to the appropriate address location.
3. The interrupt to a specific port can be set by any one of the other three ports. The appropriate control states for the other three ports are depicted above. In the
event that two or more ports attempt to set the same interrupt flag simultaneously via a valid data write, the data stored at the mailbox location will be
indeterminate.
4. A 15 is a NC for IDT70V5378, therefore Mailbox Interrupt Addresses are 7FFF, 7FFE, 7FFD and 7FFC. Address comparison will be for A 0 - A 14 .
22
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| IDT70V5388S133BG | 功能描述:IC SRAM 1.125MBIT 133MHZ 272BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT70V5388S133BG8 | 功能描述:IC SRAM 1.125MBIT 133MHZ 272BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT70V5388S166BC | 功能描述:IC SRAM 1.125MBIT 166MHZ 256BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT70V5388S166BC8 | 功能描述:IC SRAM 1.125MBIT 166MHZ 256BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| IDT70V5388S166BCI | 功能描述:IC SRAM 1.125MBIT 166MHZ 256BGA RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:3,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
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