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参数资料
| 型号： | IDT72V265LA10PFI |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 |
| 中文描述： | 3.3伏的CMOS SuperSync先进先出8192 × 18 16,384 × 18 |
| 文件页数： | 22/27页 |
| 文件大小： | 439K |
| 代理商： | IDT72V265LA10PFI |
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IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Symbol
Name
I/O
Description
D0–D17
Data Inputs
I
Data inputs for a 18-bit bus.
MRS
Master Reset
I
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two program
mable flag default settings, and serial or parallel programming of the offset settings.
PRS
PartialReset
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and
programmable flag settings are all retained.
RT
Retransmit
I
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to
LOW (
OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming
method, existing timing mode or programmable flag settings.
RT is useful to reread data from the first
physical location of the FIFO.
FWFT/SI
First Word Fall
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,
Through/Serial In
this pin functions as a serial input for loading offset registers
WCLK
WriteClock
I
When enabled by
WEN, the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming, and when enabled by
SEN, the rising edge of
WCLK writes one bit of data into the programmable register for serial programming.
WEN
Write Enable
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
Read Clock
I
When enabled by
REN, the rising edge of RCLK reads data from the FIFO memory and offsetsfrom
the programmable registers.
REN
Read Enable
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE
OutputEnable
I
OEcontrolstheoutputimpedanceofQn.
SEN
Serial Enable
I
SENenablesserialloadingofprogrammableflagoffsets.
LD
Load
I
During Master Reset,
LD selects one of two partial flag default offsets (127 or 1,023) and determines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
and reading from the offset registers.
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master Reset.
FF/IR
Full Flag/
O
In the IDT Standard mode, the
FF function is selected. FF indicates whether or not the FIFO
Input Ready
memory is full. In the FWFT mode, the
IR function is selected. IR indicates whether or not
there is space available for writing to the FIFO memory.
EF/OR
Empty Flag/
O
In the IDT Standard mode, the
EF function is selected. EF indicates whether or not the FIFO
Output Ready
memory is empty. In FWFT mode, the
OR function is selected. OR indicates whether or not there is
valid data available at the outputs.
PAF
Programmable
O
PAF goes LOW if the number of words in the FIFO memory is more than total word capacity of the
Almost-FullFlag
FIFO minus the full offset value m, which is stored in the Full Offset register. There are two possible
default values for m: 127 or 1,023.
PAE
Programmable
O
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in
Almost-EmptyFlag
the Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values
for n can be programmed into the device.
HF
Half-Full Flag
O
HF indicates whether the FIFO memory is more or less than half-full.
Q0–Q17
DataOutputs
O
Data outputs for an 18-bit bus.
VCC
Power
+3.3 Volt power supply pins.
GND
Ground
Ground pins.
PIN DESCRIPTION
相关PDF资料 |
PDF描述 |
|---|---|
| IDT72V265LA10TFI | 3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 |
| IDT72V265LA20PFI | Bus buffer/line driver; 3-state - Description: Dual Bus Buffer/Line driver 3-state ; Logic switching levels: CMOS ; Number of pins: 8 ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.4@5V ns; Voltage: 2.0-5.5 V |
| IDT72V265LA20TFI | 3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 |
| IDT72V271LA10TF | 3.3 VOLT CMOS SuperSync FIFO |
| IDT72V271LA15PF | 3.3 VOLT CMOS SuperSync FIFO |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT72V265LA10TF | 功能描述:IC FIFO SS 16384X18 10NS 64STQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V265LA10TF8 | 功能描述:IC FIFO SS 16384X18 10NS 64STQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V265LA10TFG | 功能描述:IC FIFO SS 16384X18 10NS 64STQFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V265LA10TFG8 | 功能描述:IC FIFO SS 16384X18 10NS 64STQFP RoHS:是 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
| IDT72V265LA15PF | 功能描述:IC FIFO SS 16384X18 15NS 64-TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K（16K x 18） 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP（14x14） 包装:托盘 其它名称:72271LA10PF |
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