参数资料
型号: IDT72V3612L15PQF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: FIFO
英文描述: 3.3 VOLT CMOS SyncBiFIFO-TM 64 x 36 x 2
中文描述: 64 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP132
封装: PLASTIC, QFP-132
文件页数: 12/25页
文件大小: 240K
代理商: IDT72V3612L15PQF
2
IDT72V3612 3.3V, CMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
GND
AEB
EFB
B0
B1
B2
GND
B3
B4
B5
B6
VCC
B7
B8
B9
GND
B10
B11
VCC
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23
117
17
16
15
14
13
12
11
10
9
8
7
6
4
3
2
1
132
130
129
128
127
126
125
124
123
122
121
120
119
118
131
5
GND
AEA
EFA
A0
A1
A2
GND
A3
A4
A5
A6
VCC
A7
A8
A9
GND
A10
A11
VCC
A12
A13
A14
GND
A15
A16
A17
A18
A19
A20
GND
A21
A22
A23
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
4659 drw 02
V
CC
V
CC
A
24
A
25
A
26
A
27
GND
A
28
A
29
V
CC
A
30
A
31
A
32
GND
A
33
A
34
A
35
GND
B
35
B
34
B
33
GND
B
32
B
31
B
30
V
CC
B
29
B
28
B
27
GND
B
26
B
25
B
24
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
AFB
AFA
FFA CSA ENA CLKA W/
R
A
V
CC
PGA
FS
0
ODD/
EVEN
FS
1
PEFA
MBF2
RST
NC
GND
NC
MBF1 GND PEFB
V
CC
W/
R
B
CLKB
ENB
CSB FFB
GND
MBA
MBB
PGB
NOTES:
1. NC - No internal connection
2. Uses Yamaichi socket IC51-1324-828
PQFP(2) (PQ132-1, order code: PQF)
TOP VIEW
*Electricalpin1incenterofbevelededge.Pin1identifierincorner.
*
PIN CONFIGURATIONS
and has read access times as fast as 8ns. The FIFO operates in IDT Standard
mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip
buffer data in opposite directions. Each FIFO has flags to indicate empty and
fullconditionsandtwoprogrammableflags(Almost-FullandAlmost-Empty)to
indicatewhenaselectednumberofwordsisstoredinmemory. Communication
betweeneachportcanbypasstheFIFOsviatwo36-bitmailboxregisters. Each
mailbox register has a flag to signal when new mail has been stored. Parity is
checked passively on each port and may be ignored if not desired. Parity
generation can be selected for data read from each port. Two or more devices
can be used in parallel to create wider data paths.
This device is a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the
LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bi-
directional interface between microprocessors and/or buses with synchro-
nous control.
The Full Flag (
FFA, FFB) and Almost-Full (AFA, AFB) flag of a FIFO
are two-stage synchronized to the port clock that writes data to its array.
The Empty Flag (
EFA, EFB) and Almost-Empty (AEA, AEB) flag of a
FIFO are two stage synchronized to the port clock that reads data from
its array.
The IDT72V3612 is characterized for operation from 0
°C to 70°C.
Industrial temperature range (–40
°Cto+85°C)isavailablebyspecialorder.
This device is fabricated using IDT's high speed, submicron CMOS
technology.
相关PDF资料
PDF描述
IDT72V3612L20PF 3.3 VOLT CMOS SyncBiFIFO-TM 64 x 36 x 2
IDT72V3612L20PQF 3.3 VOLT CMOS SyncBiFIFO-TM 64 x 36 x 2
IDT72V3624L10PF 3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
IDT72V3624L15PF 3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
IDT72V3626L10PF 3.3 VOLT CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
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