参数资料
型号: IDT72V3612L15PQF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: FIFO
英文描述: 3.3 VOLT CMOS SyncBiFIFO-TM 64 x 36 x 2
中文描述: 64 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP132
封装: PLASTIC, QFP-132
文件页数: 13/25页
文件大小: 240K
代理商: IDT72V3612L15PQF
20
IDT72V3612 3.3V, CMOS SyncBiFIFOTM
64 x 36 x 2
COMMERCIALTEMPERATURERANGE
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for
AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW2, then
AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (
CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
Figure 12. Timing for
AEA when FIFO2 is Almost Empty
Figure 14. Timing for
AFB when FIFO2 is Almost Full
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for
AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW2, then
AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 Write (
CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
Figure 13. Timing for
AFA when FIFO1 is Almost Full
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for
AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then
AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (
CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
AEA
CLKB
ENA
4659 drw 15
ENB
CLKA
2
1
tENS2
tENH2
tSKEW2
tPAE
tENS2
tENH2
(X+1) Words in FIFO2
X Words in FIFO2
(1)
AFA
CLKA
ENB
4659 drw 16
ENA
CLKB
12
tSKEW2
tENS2
tENH2
tPAF
tENS2
tENH2
tPAF
[64-(X+1)] Words in FIFO1
(64-X) Words in FIFO1
(1)
AFB
CLKB
ENA
4659 drw 17
ENB
CLKA
12
tSKEW2
tENS2
tENH2
tPAF
tENS2
tENH2
tPAF
[64-(X+1)] Words in FIFO2
(64-X) Words in FIFO2
(1)
相关PDF资料
PDF描述
IDT72V3612L20PF 3.3 VOLT CMOS SyncBiFIFO-TM 64 x 36 x 2
IDT72V3612L20PQF 3.3 VOLT CMOS SyncBiFIFO-TM 64 x 36 x 2
IDT72V3624L10PF 3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
IDT72V3624L15PF 3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
IDT72V3626L10PF 3.3 VOLT CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
相关代理商/技术参数
参数描述
IDT72V3612L20PF 功能描述:IC FIFO 64X36X2 20NS 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K(16K x 18) 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(14x14) 包装:托盘 其它名称:72271LA10PF
IDT72V3612L20PF8 功能描述:IC FIFO 64X36X2 20NS 120QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K(16K x 18) 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(14x14) 包装:托盘 其它名称:72271LA10PF
IDT72V3612L20PQF 功能描述:IC FIFO 64X36X2 20NS 132QFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K(16K x 18) 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(14x14) 包装:托盘 其它名称:72271LA10PF
IDT72V3613L12PF 功能描述:IC FIFO CLOCK 64X36 12NS 120TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K(16K x 18) 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(14x14) 包装:托盘 其它名称:72271LA10PF
IDT72V3613L12PF8 功能描述:IC FIFO CLOCK 64X36 12NS 120TQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:72V 标准包装:90 系列:7200 功能:同步 存储容量:288K(16K x 18) 数据速率:100MHz 访问时间:10ns 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:64-LQFP 供应商设备封装:64-TQFP(14x14) 包装:托盘 其它名称:72271LA10PF