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参数资料
| 型号： | IDT82V3010PVG8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 30/31页 |
| 文件大小： | 0K |
| 描述： | IC PLL WAN 51/E1/OC3 DUAL 56SSOP |
| 标准包装： | 1,000 |
| 类型： | 时钟/频率发生器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 电信 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，TTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 32.768MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 56-SSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 82V3010PVG8 |
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IDT82V3010
T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs
Pin Description
8
Feberuary 20, 2009
C19o
(CMOS) O
43
19.44 MHz Clock Output (CMOS Level).
This output is used for OC3/STS3 applications.
C32o
(CMOS) O
25
32.768 MHz Clock Output.
This output is a 32.768 MHz clock used for ST-BUS operation.
C16o
(CMOS) O
24
16.384 MHz Clock Output.
This output is a 16.384 MHz clock used for ST-BUS operation.
C8o
(CMOS) O
23
8.192 MHz Clock Output.
This output is an 8.192 MHz clock used for ST-BUS operation.
C4o
(CMOS) O
20
4.096 MHz Clock Output.
This output is a 4.096 MHz clock used for ST-BUS operation.
C2o
(CMOS) O
17
2.048 MHz Clock Output.
This output is a 2.048 MHz clock used for ST-BUS operation.
C3o
(CMOS) O
16
3.088 MHz Clock Output.
This output is used for T1 applications.
C1.5o
(CMOS) O
15
1.544 MHz Clock Output.
This output is used for T1 applications.
C6o
(CMOS) O
14
6.312 MHz Clock Output.
This output is used for DS2 applications.
C2/C1.5
(CMOS) O
54
2.048 MHz or 1.544 MHz Clock Output.
This output is a 2.048 MHz or 1.544 MHz clock signal. If the selected reference input (Fref0 or Fref1) is 8 kHz, 2.048
MHz, or 19.44 MHz, the C2/C1.5 pin will output a 2.048 MHz clock signal. If the frequency of the selected reference
input (Fref0 or Fref1) is 1.544 MHz, the C2/C1.5 pin will output a 1.544 MHz clock signal. Refer to Table - 5 for
details.
F19o
(CMOS) O
49
8 kHz Frame Signal with 19.44 MHz Pulse Width.
This output is used for OC3/STS3 applications.
F32o
(CMOS) O
40
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 30 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This framing signal
is typically used for ST-BUS operation at 8.192 Mb/s.
F16o
(CMOS) O
39
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 61 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This framing signal
is typically used for ST-BUS operation at 8.192 Mb/s.
F8o
(CMOS) O
36
Frame Pulse.
This is an 8 kHz 122 ns active high framing pulse, which marks the beginning of a frame.
F0o
(CMOS) O
33
Frame Pulse ST-BUS 2.048 Mb/s.
This is an 8 kHz 244 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This framing
signal is typically used for ST-BUS operation at 2.048 Mb/s and 4.096 Mb/s.
RSP
(CMOS) O
41
Receive Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of a ST-BUS frame. This framing
signal is typically used to connect to the Siemens MUNICH-32 device.
TSP
(CMOS) O
42
Transmit Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This framing is
typically used to connect to the Siemens MUNICH-32 device.
TDO
(CMOS) O
29
Test Serial Data Out.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when
JTAG scan is not enabled.
TDI
I32
Test Serial Data In.
JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VDDD.
TRST
I30
Test Reset.
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is internally
pulled up to VDDD. It is connected to the ground for normal applications.
TCK
I28
Test Clock.
Provides the clock for the JTAG test logic.
TMS
I31
Test Mode Select.
JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDDD.
IC0, IC2
-
53, 55
These pins should be connected to VSS.
Name
Type
Pin Number
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82V3011 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT |
| IDT82V3011PV | 制造商:INT_DEV_TECH 功能描述: |
| IDT82V3011PVG | 功能描述:IC PLL WAN T1/E1/OC3 SGL 56-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3011PVG8 | 功能描述:IC PLL WAN T1/E1/OC3 SGL 56-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3012 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS |
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