IDT82V3010PVG8 (IDT,) PDF资料下载 Datasheet(4/31 页)

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参数资料

型号：	IDT82V3010PVG8
厂商：	IDT, Integrated Device Technology Inc
文件页数：	4/31页
文件大小：	0K
描述：	IC PLL WAN 51/E1/OC3 DUAL 56SSOP
标准包装：	1,000
类型：	时钟/频率发生器，多路复用器
PLL：	是
主要目的：	电信
输入：	时钟
输出：	CMOS，LVDS，TTL
电路数：	1
比率 - 输入:输出：	2:12
差分 - 输入:输出：	无/是
频率 - 最大：	32.768MHz
电源电压：	3 V ~ 3.6 V
工作温度：	-40°C ~ 85°C
安装类型：	表面贴装
封装/外壳：	56-BSSOP（0.295"，7.50mm 宽）
供应商设备封装：	56-SSOP
包装：	带卷 (TR)
其它名称：	82V3010PVG8

IDT82V3010

T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs

Functional Description

Feberuary 20, 2009

Figure - 5 Reference Switch with TIE Control Block Enabled

Figure - 6 Reference Switch with TIE Control Block Disabled

2.7

DPLL BLOCK

As shown in Figure - 7, the DPLL Block consists of a Phase Detector,

a Limiter, a Loop Filter, a Digital Control Oscillator and Divider.

2.7.1

PHASE DETECTOR (PHD)

In the Normal mode, the Phase Detector compares the virtual

reference signal from the TIE Control Circuit with the feedback signal

from the Frequency Select Circuit, and outputs an error signal

corresponding to the phase difference. This error signal is sent to the

Limiter circuit for phase slope control.

In the Freerun or Holdover mode, the Frequency Select Circuit, the

Phase Detector and the Limiter are inactive, and the input reference

signal is not used.

2.7.2

LIMITER

The Limiter is used to limit the phase slope. It ensures that the

maximum output phase slope is limited to 5 ns per 125 s for all input

transient conditions. This well meets the AT&T TR62411specification

which specify the maximum phase slope of 7.6 ns per 125 s.

Input Clock

Ref1

Ref2

Time = 0.00 s

Time = 0.25 s

Time = 0.50 s

Time = 0.75 s

Time = 1.0 s

Time = 1.25 s

Time = 1.50 s

Time = 1.75 s

Output Clock